公开(公告)号：US20240222218A1

公开(公告)日：2024-07-04

申请号：US18604957

申请日：2024-03-14

申请人： Taiwan Semiconductor Manufacturing Co, Ltd.

发明人： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC分类号： H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

摘要： A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US11961779B2

公开(公告)日：2024-04-16

申请号：US17331945

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC分类号： H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/291 ,  H01L2924/014

摘要： A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US20240079366A1

公开(公告)日：2024-03-07

申请号：US18454217

申请日：2023-08-23

申请人： Samsung Electronics Co., Ltd.

发明人： Jonggyu Lee ,  Jaechoon Kim ,  Taehwan Kim ,  Hwanjoo Park

IPC分类号： H01L23/00 ,  H01L23/36 ,  H01L25/065

CPC分类号： H01L24/33 ,  H01L23/36 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/065 ,  H01L2924/16235 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/165

摘要： A semiconductor package includes a package substrate, a semiconductor chip on the package substrate and having a first surface facing the package substrate and a second surface, opposite to the first surface, an encapsulant disposed on the package substrate and on a side surface of the semiconductor chip, a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip, a bonding enhancing layer on the second surface of the semiconductor chip, a thermal interface material layer on the bonding enhancing layer and in a gap between the bonding enhancing layer and the heat dissipation member, wherein the thermal interface material layer includes liquid metal, and a porous barrier structure formed of a metal material and surrounding the bonding enhancing layer and the thermal interface material layer.

公开(公告)号：US10083940B2

公开(公告)日：2018-09-25

申请号：US15622166

申请日：2017-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L23/58 ,  H01L25/03 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/34

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/585 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/26125 ,  H01L2224/26145 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81007 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.

公开(公告)号：US20240363577A1

公开(公告)日：2024-10-31

申请号：US18357596

申请日：2023-07-24

申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.

发明人： Pin-Jing SU ,  Wen-Yu TENG ,  Liang-Yi HUNG ,  Chia-Cheng CHEN ,  Yu-Po WANG

IPC分类号： H01L23/00 ,  H01L23/367

CPC分类号： H01L24/32 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1611 ,  H01L2924/16235 ,  H01L2924/1632

摘要： An electronic package and a substrate structure thereof are provided, in which an electronic element and a flow stopper surrounding the electronic element are disposed on a substrate body of the substrate structure, and a heat dissipation structure is bonded on the electronic element via a heat dissipation material, so that the flow stopper limits an overflow range of the heat dissipation material to prevent the heat dissipation material from contaminating a circuit layer on the substrate body.

公开(公告)号：US11955441B2

公开(公告)日：2024-04-09

申请号：US17706039

申请日：2022-03-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L27/02 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L21/76805 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

摘要： An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

公开(公告)号：US20180218962A1

公开(公告)日：2018-08-02

申请号：US15748475

申请日：2015-08-31

申请人： INTEL IP CORPORATION

发明人： Christian GEISSLER ,  Georg SEIDEMANN ,  Sonja KOLLER ,  Jan PROSCHWITZ

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/563 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/073 ,  H01L25/074 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32141 ,  H01L2224/32507 ,  H01L2224/33519 ,  H01L2924/15153

摘要： Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.

公开(公告)号：US20170278827A1

公开(公告)日：2017-09-28

申请号：US15622166

申请日：2017-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/03

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/585 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/26125 ,  H01L2224/26145 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81007 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.

公开(公告)号：US09685426B2

公开(公告)日：2017-06-20

申请号：US15170036

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L25/065 ,  H01L23/34 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/58 ,  H01L23/31 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L25/03

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/585 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/26125 ,  H01L2224/26145 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81007 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate and a first die coupled to a top surface of the substrate. A second die is coupled to a bottom surface of the substrate. A thermal contact pad couples the second die to the bottom surface of the substrate. The thermal contact pad electrically isolates the first die from the second die. A molding compound resides over the substrate and surrounds the first and second dies and the thermal contact pad.

公开(公告)号：US20240213180A1

公开(公告)日：2024-06-27

申请号：US18602392

申请日：2024-03-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jian-Hong LIN ,  Kuo-Yen LIU ,  Hsin-Chun CHANG ,  Tzu-Li LEE ,  Yu-Ching LEE ,  Yih-Ching WANG

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58 ,  H01L27/02

CPC分类号： H01L23/562 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L21/76805 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

摘要： An interconnect structure includes a first dielectric layer, a first metal layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer and has a first segment and a second segment separated from the first segment. The metal via includes a first portion between the first and second segments of the first metal layer, and a second portion above the first metal layer. The second metal layer is over the metal via. From a top view, the second metal layer includes a metal line extending across the first and second segments of the first metal layer. From a cross-sectional view, the first portion of the metal via has opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via.