公开(公告)号：US20170236761A1

公开(公告)日：2017-08-17

申请号：US15174450

申请日：2016-06-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yu-Te HSIEH

IPC: H01L23/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/302 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/10 ,  H01L21/302 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/525 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/29021 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29099 ,  H01L2224/32013 ,  H01L2224/32111 ,  H01L2224/32112 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/325 ,  H01L2224/83193 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/16235 ,  H01L2924/1632 ,  H01L2924/1659 ,  H01L2924/16788 ,  H01L2224/13099

Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

公开(公告)号：US09693462B2

公开(公告)日：2017-06-27

申请号：US14790556

申请日：2015-07-02

Applicant: Mitsubishi Electric Corporation

Inventor： Takeshi Hosomi

IPC: H05K1/18 ,  H05K3/46 ,  H01L33/62 ,  H01L23/10 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H05K7/00 ,  H05K1/02 ,  H01L27/146 ,  H01L23/367 ,  H01L23/00 ,  H01L25/16

CPC classification number: H05K1/183 ,  H01L23/10 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L25/167 ,  H01L27/14618 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/142 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0206 ,  H05K1/021 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/1056 ,  H05K2203/304 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/48247 ,  H01L2924/00

Abstract: A printed circuit board includes: a printed wiring board including an insulating layer wherein a recessed part is provided on a top surface of the insulating layer, and a printed conductor provided inside the recessed part; a bare chip part mounted in the recessed part and electrically connected to the printed conductor; an electronic part mounted on the top surface of the printed wiring board other than the recessed part; and a cap fixed to the top surface of the printed wiring board and hollow-sealing the bare chip part mounted in the recessed part, wherein using a height of the top surface of the printed wiring board as a reference, a height of a top surface of the cap is equal to or below a maximum height of a top surface of the electronic part.

公开(公告)号：US09425115B2

公开(公告)日：2016-08-23

申请号：US14104658

申请日：2013-12-12

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Ruben B. Montez ,  Robert F. Steimle

IPC: H01L23/10 ,  H01L23/04 ,  H01L21/74 ,  H01L23/00

CPC classification number: H01L23/10 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L21/743 ,  H01L23/04 ,  H01L23/053 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16788 ,  H01L2924/00

Abstract: A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

Abstract translation: 一种键合半导体器件，包括支撑衬底，相对于所述支撑衬底的一侧定位的半导体器件，覆盖所述支撑衬底和所述器件的帽衬底，所述支撑衬底和所述帽衬底之间的玻璃料接合环，电 支撑基板和盖基板之间的导电环。 导电环在半导体器件周围形成内环，并且玻璃料接合环在半导体器件周围形成外部结合环。

公开(公告)号：US20160143148A1

公开(公告)日：2016-05-19

申请号：US14790556

申请日：2015-07-02

Applicant: Mitsubishi Electric Corporation

Inventor： Takeshi HOSOMI

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/183 ,  H01L23/10 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L25/167 ,  H01L27/14618 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/142 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0206 ,  H05K1/021 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/1056 ,  H05K2203/304 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/48247 ,  H01L2924/00

Abstract: A printed circuit board includes: a printed wiring board including an insulating layer wherein a recessed part is provided on a top surface of the insulating layer, and a printed conductor provided inside the recessed part; a bare chip part mounted in the recessed part and electrically connected to the printed conductor; an electronic part mounted on the top surface of the printed wiring board other than the recessed part; and a cap fixed to the top surface of the printed wiring board and hollow-sealing the bare chip part mounted in the recessed part, wherein using a height of the top surface of the printed wiring board as a reference, a height of a top surface of the cap is equal to or below a maximum height of a top surface of the electronic part.

Abstract translation: 印刷电路板包括：印刷布线板，包括绝缘层，其中在绝缘层的顶表面上设置凹部，以及设置在凹部内的印刷导体; 裸芯片部分安装在凹部中并电连接到印刷导体; 安装在所述印刷电路板的除了所述凹部以外的上表面的电子部件; 以及固定在印刷电路板的上表面上的盖，对安装在凹部中的裸芯片部进行中空密封，其中以印刷电路板的上表面的高度为基准，上表面的高度 的盖子等于或低于电子部件顶表面的最大高度。

公开(公告)号：US20150277068A1

公开(公告)日：2015-10-01

申请号：US14687119

申请日：2015-04-15

Applicant: Cisco Technology, Inc.

Inventor： Kishor DESAI ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

IPC: G02B6/42 ,  G02B6/13

CPC classification number: G02B6/4255 ,  G02B6/12 ,  G02B6/13 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H01L21/50 ,  H01L23/04 ,  H01L23/48 ,  H01L25/167 ,  H01L31/0203 ,  H01L33/52 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/165 ,  H01L2924/16788 ,  H05K1/0268 ,  H05K1/0274 ,  H05K2201/10121 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract translation: 提供了一种光电子组件，其包括用于支撑多个互连的光学和电气部件的基板（通常为硅或玻璃）。 设置一层密封材料以概述衬底的限定的周边区域。 将模制的玻璃盖设置在基底上并结合到基底上，其中模制的玻璃盖构造成产生与限定的基底周边区域匹配的覆盖区。 模制玻璃盖的底表面包括一层接合材料，其在接触时接触基底的密封材料层，形成结合组件。 在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。

公开(公告)号：US09018753B2

公开(公告)日：2015-04-28

申请号：US13958146

申请日：2013-08-02

Applicant: STMicroelectronics Pte Ltd.

Inventor： Wing Shenq Wong

IPC: H01L23/12 ,  H01L23/22 ,  H01L23/24 ,  H01L23/04 ,  H01L21/82 ,  H01L23/00 ,  H01L21/10

CPC classification number: H01L23/04 ,  H01L21/10 ,  H01L21/82 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.

Abstract translation: 描述了一种用于制造电子模块的方法，包括将限定多个空腔的矩阵面板模制到基板上，将半导体管芯附着到模制矩阵面板的相应空腔中的基板面板，将半导体管芯电连接到基板面板， 模制矩阵面板的盖子以形成电子模块组件，将电子模块组件安装在载带上，以及将电子模块组件分离成各个电子模块。 描述了一种电子模块，其包括衬底，模制在衬底上的壁构件，限定空腔的模制壁构件，至少一个连接到空腔中的衬底并电连接到衬底的半导体管芯，以及固定到 模制的壁构件在空腔上。

公开(公告)号：US20130021767A1

公开(公告)日：2013-01-24

申请号：US13239287

申请日：2011-09-21

Applicant: KAI-WEN WU

Inventor： KAI-WEN WU

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H01L23/16 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/16195 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4611 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A double-sided PCB includes a circuit plate, a first chip, and a second chip. The circuit plate includes a spacer layer having a first surface and an opposing second surface, a first multilayer structure, and a second multilayer structure. The first multilayer structure includes a first wire layer, a first middle layer, and a second wire layer having a first grounding portion and first conductive pattern portions, that are stacked on each other on the first surface. The second multilayer structure on the second surface is either a mirror image of the first multilayer structure, or is very similar thereto. The first and second chips are each arranged on a grounding portion and are each electrically connected to their respective conductive pattern portions.

Abstract translation: 双面PCB包括电路板，第一芯片和第二芯片。 电路板包括具有第一表面和相对的第二表面的间隔层，第一多层结构和第二多层结构。 第一多层结构包括第一线层，第一中间层和具有第一接地部分和第一导电图案部分的第二导线层，第一接地部分和第一导电图案部分在第一表面上彼此堆叠。 第二表面上的第二多层结构是第一多层结构的镜像，或与其非常相似。 第一和第二芯片各自布置在接地部分上，并且各自电连接到它们各自的导电图案部分。

公开(公告)号：US08101469B2

公开(公告)日：2012-01-24

申请号：US12732689

申请日：2010-03-26

Applicant: G. Krishna Kumar ,  Nishit A. Choksi ,  Joseph M. Chalil

Inventor： G. Krishna Kumar ,  Nishit A. Choksi ,  Joseph M. Chalil

IPC: H01L21/44

CPC classification number: H01L25/18 ,  B81C1/0023 ,  B81C1/00238 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/24227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Abstract translation: 一种形成单片CMOS-MEMS混合集成封装结构的方法包括以下步骤：提供至少一个具有包括电介质层和金属化层的CMOS器件区域的半导体衬底; 施加覆盖在CMOS器件区域上的至少一个保护层; 在所述保护层上形成至少一个开口，并且对所述电介质层和金属化层进行图形化以进入所述半导体衬底; 通过蚀刻所述电介质层和金属化层在所述半导体衬底上形成至少一个开口; 在所述半导体衬底上的所述至少一个开口中施加至少一个填充层; 将至少一个芯片定位在填充层上，该芯片包括预制的正面和裸露的背面; 施加覆盖芯片前表面的第一绝缘层，从半导体衬底到芯片提供连续性; 在覆盖芯片的绝缘层上形成至少一个通孔，以进入至少一个接触区域; 施加覆盖在所述衬底上的所述绝缘层上的至少一个金属化层和将所述衬底上的所述金属化层连接到所述芯片上的所述至少另一个接触区域中的所述芯片; 在所述至少一个芯片上施加覆盖所述金属化层的第二绝缘层; 施加至少一个界面层; 施加覆盖在界面层上的至少一个刚性基材; 以及施加覆盖在刚性基材上的至少一个二次保护层。

公开(公告)号：US20180082913A1

公开(公告)日：2018-03-22

申请号：US15823744

申请日：2017-11-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yu-Te HSIEH

IPC: H01L23/10 ,  H01L23/00 ,  H01L21/302 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/10 ,  H01L21/302 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/525 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/29021 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29099 ,  H01L2224/32013 ,  H01L2224/32111 ,  H01L2224/32112 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/325 ,  H01L2224/83193 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/16235 ,  H01L2924/1632 ,  H01L2924/1659 ,  H01L2924/16788 ,  H01L2224/13099

Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

公开(公告)号：US09575266B2

公开(公告)日：2017-02-21

申请号：US14687119

申请日：2015-04-15

Applicant: Cisco Technology, Inc.

Inventor： Kishor Desai ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

IPC: G02B6/12 ,  G02B6/42 ,  H01L33/52 ,  G02B6/43 ,  H01L23/04 ,  H01L23/48 ,  H01L25/16 ,  H01L31/0203 ,  G02B6/13 ,  H05K1/02 ,  H01L21/50

CPC classification number: G02B6/4255 ,  G02B6/12 ,  G02B6/13 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H01L21/50 ,  H01L23/04 ,  H01L23/48 ,  H01L25/167 ,  H01L31/0203 ,  H01L33/52 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/165 ,  H01L2924/16788 ,  H05K1/0268 ,  H05K1/0274 ,  H05K2201/10121 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract translation: 提供了一种光电子组件，其包括用于支撑多个互连的光学和电气部件的基板（通常为硅或玻璃）。 设置一层密封材料以概述衬底的限定的周边区域。 将模制的玻璃盖设置在基底上并结合到基底上，其中模制的玻璃盖构造成产生与限定的基底周边区域匹配的覆盖区。 模制玻璃盖的底表面包括一层接合材料，其在接触时接触基底的密封材料层，形成结合组件。 在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。