公开(公告)号：US12136608B2

公开(公告)日：2024-11-05

申请号：US18166931

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong Chen ,  David Gani

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/16

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US11848378B2

公开(公告)日：2023-12-19

申请号：US17373198

申请日：2021-07-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Ditto Adnan ,  Maurizio Gabriele Castorina ,  Voon Cheng Ngwan ,  Fadhillawati Tahir

IPC: H01L29/78 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/765 ,  H01L29/401 ,  H01L29/407 ,  H01L29/66734

Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

公开(公告)号：US11774422B2

公开(公告)日：2023-10-03

申请号：US16458561

申请日：2019-07-01

Applicant: STMicroelectronics PTE LTD

Inventor： Fangxing Yuan ,  Ravi Shankar ,  Olivier Le Neel

IPC: G01N33/00 ,  G01N29/22

CPC classification number: G01N33/0013 ,  G01N29/228 ,  G01N33/0016 ,  G01N33/0031

Abstract: The present disclosure is directed to a selective multi-gas sensor device that detects when a high concentration level of a particular gas, such as methane, carbon monoxide, and/or ethanol, is present. The selective multi-gas sensor device detects and identifies a particular gas based on a ratio between a sensitivity of a gas sensitive material at a first temperature and a sensitivity of the gas sensitive material at a second temperature.

公开(公告)号：US20230268421A1

公开(公告)日：2023-08-24

申请号：US18168509

申请日：2023-02-13

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

Inventor： Vincenzo ENEA ,  Voon Cheng NGWAN

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/66734 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/7813 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66727

Abstract: A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).

公开(公告)号：US20230197545A1

公开(公告)日：2023-06-22

申请号：US18166922

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/293 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0655 ,  H01L2224/02371

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

公开(公告)号：US11502029B2

公开(公告)日：2022-11-15

申请号：US16927776

申请日：2020-07-13

Applicant: STMICROELECTRONICS PTE LTD ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent Herard ,  David Parker ,  David Gani

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/3065

Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

公开(公告)号：US20220320332A1

公开(公告)日：2022-10-06

申请号：US17694276

申请日：2022-03-14

Applicant: STMicroelectronics Pte Ltd

Inventor： Yean Ching YONG ,  Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN ,  Ditto ADNAN ,  Fadhillawati TAHIR ,  Churn Weng YIM

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/764 ,  H01L21/765 ,  H01L29/66

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

公开(公告)号：US11430765B2

公开(公告)日：2022-08-30

申请号：US16795099

申请日：2020-02-19

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jian Zhou

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/10 ,  H01L21/50

Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.

公开(公告)号：US11366156B2

公开(公告)日：2022-06-21

申请号：US16746201

申请日：2020-01-17

Applicant: STMicroelectronics Pte Ltd

Inventor： Pedro Jr Santos Peralta ,  David Gani

IPC: G01R31/28 ,  H01L21/66 ,  G01R31/3185 ,  G01R31/26

Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

公开(公告)号：US20220165699A1

公开(公告)日：2022-05-26

申请号：US17522717

申请日：2021-11-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00

Abstract: The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device. The plurality of conductive layers on the plurality of raised portions or the single raised portion may be formed by a laser direct structuring (LDS) process.