Invention Grant
- Patent Title: Thin semiconductor chip using a dummy sidewall layer
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Application No.: US16927776Application Date: 2020-07-13
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Publication No.: US11502029B2Publication Date: 2022-11-15
- Inventor: Laurent Herard , David Parker , David Gani
- Applicant: STMICROELECTRONICS PTE LTD , STMICROELECTRONICS (ROUSSET) SAS
- Applicant Address: SG Singapore; FR Rousset
- Assignee: STMICROELECTRONICS PTE LTD,STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee: STMICROELECTRONICS PTE LTD,STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee Address: SG Singapore; FR Rousset
- Agency: Seed IP Law Group LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48 ; H01L21/3065

Abstract:
The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.
Public/Granted literature
- US20210020555A1 METHOD OF MANUFACTURING A THIN SEMICONDUCTOR CHIP USING A DUMMY SIDEWALL LAYER AND A DEVICE THEREOF Public/Granted day:2021-01-21
Information query
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