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公开(公告)号：US12052928B2
公开(公告)日：2024-07-30
申请号：US17397067
申请日：2021-08-09
发明人： Jijun Sun
CPC分类号： H10N50/10 , G11C11/161 , H01F10/3254 , H01F10/3272 , H10B61/20 , H10N50/80 , H10N50/85
摘要： A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).
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公开(公告)号：US12020770B2
公开(公告)日：2024-06-25
申请号：US18189738
申请日：2023-03-24
发明人： Syed M. Alam
CPC分类号： G11C7/1069 , G11C5/146 , G11C7/1045 , G11C7/1096
摘要： 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
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公开(公告)号：US20240188449A1
公开(公告)日：2024-06-06
申请号：US18438174
申请日：2024-02-09
发明人： Han-Jong CHIA
CPC分类号： H10N50/80 , G11C11/161 , G11C11/1675 , H01F10/3272 , H01F10/3286 , H01F10/329 , H10B61/22 , H10N50/85
摘要： Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device.
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公开(公告)号：US20230380297A1
公开(公告)日：2023-11-23
申请号：US18360564
申请日：2023-07-27
发明人： Jijun SUN , Jon SLAUGHTER , Renu WHIG
摘要： A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.
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公开(公告)号：US20230243898A1
公开(公告)日：2023-08-03
申请号：US18298646
申请日：2023-04-11
发明人： Phillip G. MATHER , Anuraag MOHAN
IPC分类号： G01R33/09
CPC分类号： G01R33/093 , G01R33/098
摘要： Various means for improvement in signal-to-noise ratio (SNR) for a magnetic field sensor are disclosed for low power and high resolution magnetic sensing. The improvements may be done by reducing parasitic effects, increasing sense element packing density, interleaving a Z-axis layout to reduce a subtractive effect, and optimizing an alignment between a Z-axis sense element and a flux guide, etc.
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公开(公告)号：US11651802B1
公开(公告)日：2023-05-16
申请号：US17455292
申请日：2021-11-17
发明人： Syed M. Alam
CPC分类号： G11C7/1069 , G11C5/146 , G11C7/1045 , G11C7/1096
摘要： The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
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公开(公告)号：US20220343030A1
公开(公告)日：2022-10-27
申请号：US17660253
申请日：2022-04-22
发明人： Syed M. ALAM , Sanjeev AGGARWAL
摘要： The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.
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公开(公告)号：US11436087B2
公开(公告)日：2022-09-06
申请号：US15993046
申请日：2018-05-30
摘要： The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes receiving data to be stored in a storage memory, wherein the storage memory is coupled to the memory device, wherein the memory device includes a first memory type and a second memory type different from the first memory type; storing a first copy of the received data in the first memory type; storing a second copy of the received data in the second memory type; receiving indication of a power loss to the memory device; in response to receiving indication of the power loss, copying the second copy from the second memory type to the storage memory; detecting for power restoration to the memory device after the power loss; and in response to detecting power restoration to the memory device, restoring data to the first memory type by copying data from the second memory type to the first memory type.
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公开(公告)号：US20220260651A1
公开(公告)日：2022-08-18
申请号：US17735185
申请日：2022-05-03
摘要： A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor includes a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each TMR element. The current lines are serially or sequentially connected to a current source to receive the bipolar current pulse. The field sensor has an output including a high output and a low output in response to the bipolar pulse. This asymmetric response allows a chopping technique for 1/f noise reduction in the field sensor.
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公开(公告)号：US11176974B2
公开(公告)日：2021-11-16
申请号：US16518146
申请日：2019-07-22
发明人： Syed M. Alam , Thomas S. Andre
摘要： In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
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