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公开(公告)号：US20220343030A1
公开(公告)日：2022-10-27
申请号：US17660253
申请日：2022-04-22
发明人： Syed M. ALAM , Sanjeev AGGARWAL
摘要： The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.
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公开(公告)号：US20210119118A1
公开(公告)日：2021-04-22
申请号：US17109318
申请日：2020-12-02
摘要： A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
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公开(公告)号：US20210111223A1
公开(公告)日：2021-04-15
申请号：US17131926
申请日：2020-12-23
发明人： Jijun SUN , Sanjeev AGGARWAL , Han-Jong CHIA , Jon M. SLAUGHTER , Renu WHIG
摘要： A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).
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公开(公告)号：US20210083174A1
公开(公告)日：2021-03-18
申请号：US16572982
申请日：2019-09-17
摘要： An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.
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公开(公告)号：US20230403943A1
公开(公告)日：2023-12-14
申请号：US18456293
申请日：2023-08-25
摘要： A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US20230403011A1
公开(公告)日：2023-12-14
申请号：US18329793
申请日：2023-06-06
发明人： Syed M. ALAM , Sanjeev AGGARWAL
IPC分类号： H03K19/1776 , H10B61/00 , H01L23/498 , H10N50/10 , H01L23/48
CPC分类号： H03K19/1776 , H10B61/00 , H01L23/49816 , H10N50/10 , H01L23/481
摘要： A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.
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公开(公告)号：US20220336734A1
公开(公告)日：2022-10-20
申请号：US17659234
申请日：2022-04-14
发明人： Sanjeev AGGARWAL , Kerry NAGEL , Santosh KARRE
摘要： A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.
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公开(公告)号：US20200286950A1
公开(公告)日：2020-09-10
申请号：US16881958
申请日：2020-05-22
摘要： Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US20200235288A1
公开(公告)日：2020-07-23
申请号：US16744963
申请日：2020-01-16
发明人： Sumio IKEGAWA , Han Kyu LEE , Sanjeev AGGARWAL , Jijun SUN , Syed M. ALAM , Thomas ANDRE
摘要： The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
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公开(公告)号：US20200176672A1
公开(公告)日：2020-06-04
申请号：US16695396
申请日：2019-11-26
IPC分类号： H01L43/04 , H01L43/14 , H01L21/3065
摘要： A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region. An insulator region may extend around a portion of the sidewall such that the insulator region contacts a first portion of the sidewall and the spin Hall channel region contacts a second portion of the sidewall.
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