公开(公告)号：US11763140B2

公开(公告)日：2023-09-19

申请号：US17394671

申请日：2021-08-05

Applicant: Intel Corporation

Inventor： Tomer Schwartz ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/06 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

公开(公告)号：US20220058469A1

公开(公告)日：2022-02-24

申请号：US17394671

申请日：2021-08-05

Applicant: Intel Corporation

Inventor： TOMER SCHWARTZ ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

公开(公告)号：US11093822B2

公开(公告)日：2021-08-17

申请号：US15499896

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190180168A1

公开(公告)日：2019-06-13

申请号：US16266880

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/50

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US09536342B2

公开(公告)日：2017-01-03

申请号：US14461047

申请日：2014-08-15

Applicant: INTEL CORPORATION

Inventor： Uzi Sarel ,  Tomer Bar-On ,  Jacob Subag

IPC: G06T15/20 ,  G06T15/80 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06T15/005 ,  G06F9/455

Abstract: Automatic partitioning techniques for multi-phase pixel shading are described. In an example embodiment, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more respective suitability metrics for each of one or more candidate partitioning policies for a set of pixel shader inputs for a graphics frame, each candidate partitioning policy comprising one or more rules for partitioning the set of pixel shader inputs for multi-phase pixel shading based on quality sensitivity values for the pixel shader inputs, select a partitioning policy for the set of pixel shader inputs from among the one or more candidate partitioning policies based on the determined suitability metrics, and construct a multi-phase pixel shader for the graphics frame by partitioning the set of pixel shader inputs into multiple classes according to the selected partitioning policy. Other embodiments are described and claimed.

Abstract translation: 描述了多相像素着色的自动划分技术。 在示例实施例中，装置可以包括其硬件中的至少一部分的逻辑，用于为图形的一组像素着色器输入确定一个或多个候选分区策略中的每一个的一个或多个相应的适合性度量的逻辑 帧，每个候选分区策略包括用于基于用于像素着色器输入的质量敏感度值来分割用于多相位像素着色的多个像素着色器输入的集合的一个或多个规则，从所述像素着色器输入的集合中选择所述像素着色器输入的分区策略 基于所确定的适合性度量的一个或多个候选分区策略，并且根据所选择的分区策略，将所述像素着色器输入集合划分为多个类，从而构建用于所述图形帧的多相像素着色器。 描述和要求保护其他实施例。

公开(公告)号：US20240160910A1

公开(公告)日：2024-05-16

申请号：US18527734

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US11704564B2

公开(公告)日：2023-07-18

申请号：US17404153

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/00 ,  G06N20/10

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11620766B2

公开(公告)日：2023-04-04

申请号：US17344639

申请日：2021-06-10

Applicant: INTEL CORPORATION

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/084 ,  G06N3/088

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer.

公开(公告)号：US11562200B2

公开(公告)日：2023-01-24

申请号：US16266880

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06N3/04 ,  G06F30/33

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US20220067496A1

公开(公告)日：2022-03-03

申请号：US17398302

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.