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    Iterative estimation hardware
    2.
    发明授权
    Iterative estimation hardware 有权

    公开(公告)号：US11422802B2

    公开(公告)日：2022-08-23

    申请号：US16725378

    申请日：2019-12-23

    Applicant: Imagination Technologies Limited

    Inventor： Thomas Rose ,  Max Freiburghaus ,  Robert McKemey

    IPC: G06F7/552 ,  G06F9/30 ,  G06F7/48 ,  G06F7/50 ,  G06F7/57

    Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 ⁢ / ⁢ d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

    Floating Point Adder
    3.
    发明公开
    Floating Point Adder 审中-公开

    公开(公告)号：US20230176817A1

    公开(公告)日：2023-06-08

    申请号：US17989926

    申请日：2022-11-18

    Applicant: Imagination Technologies Limited

    Inventor： Max Freiburghaus

    IPC: G06F7/485

    CPC classification number: G06F7/485

    Abstract: An adder and a method for calculating 2n+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2n+x for x

    Verifying a Hardware Design for a Component that Implements a Permutation Respecting Function
    4.
    发明申请
    Verifying a Hardware Design for a Component that Implements a Permutation Respecting Function 审中-公开

    公开(公告)号：US20190303511A1

    公开(公告)日：2019-10-03

    申请号：US16367493

    申请日：2019-03-28

    Applicant: Imagination Technologies Limited

    Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

    IPC: G06F17/50

    Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

    Verifying a hardware design for a component that implements a permutation respecting function
    5.
    发明授权
    Verifying a hardware design for a component that implements a permutation respecting function 有权

    公开(公告)号：US11455451B2

    公开(公告)日：2022-09-27

    申请号：US16367493

    申请日：2019-03-28

    Applicant: Imagination Technologies Limited

    Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

    IPC: G06F30/3323 ,  G06F30/33 ,  G06F119/18

    Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

    VERIFICATION OF HARDWARE DESIGN FOR INTEGRATED CIRCUIT IMPLEMENTING POLYNOMIAL INPUT VARIABLE FUNCTION
    6.
    发明申请
    VERIFICATION OF HARDWARE DESIGN FOR INTEGRATED CIRCUIT IMPLEMENTING POLYNOMIAL INPUT VARIABLE FUNCTION 有权

    公开(公告)号：US20210350057A1

    公开(公告)日：2021-11-11

    申请号：US17384483

    申请日：2021-07-23

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

    IPC: G06F30/3323

    Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

    Verification of Hardware Design for Integrated Circuit Implementing Polynomial Input Variable Function
    7.
    发明申请
    Verification of Hardware Design for Integrated Circuit Implementing Polynomial Input Variable Function 审中-公开

    公开(公告)号：US20200327270A1

    公开(公告)日：2020-10-15

    申请号：US16848934

    申请日：2020-04-15

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott ,  Robert McKemey ,  Max Freiburghaus

    IPC: G06F30/3323

    Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

    EFFICIENT FLOATING POINT SQUARER
    9.
    发明公开
    EFFICIENT FLOATING POINT SQUARER 审中-公开

    公开(公告)号：US20240134602A1

    公开(公告)日：2024-04-25

    申请号：US18240618

    申请日：2023-08-31

    Applicant: Imagination Technologies Limited

    Inventor： Max Freiburghaus ,  William Wheeler ,  Daniel Ley

    IPC: G06F7/487

    CPC classification number: G06F7/4876

    Abstract: Methods of squaring, in hardware logic, a floating point number comprising an m-bit input exponent and an input mantissa comprise generating a candidate mantissa output, in mantissa hardware logic, by squaring the input mantissa and generating, in exponent and exception logic, three candidate exponent outputs. The three candidate exponent outputs comprise (i) an exceptional exponent output, (ii) an exponent output generated from the m-bit input exponent and (iii) an incremental exponent generated by incrementing the exponent output. The method further comprises selecting, as the output mantissa, either the candidate mantissa output or an exceptional mantissa output based on exception signals generated by the exponent and exception logic based on the m-bit input exponent. The method additionally comprises selecting, as an output exponent, one of the three candidate exponent outputs based on the exception signals and based on a signal indicating a mantissa overflow condition.

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