Transformer failure diagnosis method and system based on integrated deep belief network

    公开(公告)号:US12131247B2

    公开(公告)日:2024-10-29

    申请号:US17126067

    申请日:2020-12-18

    申请人: WUHAN UNIVERSITY

    IPC分类号: G06N3/047 G06F17/14 G06N3/08

    CPC分类号: G06N3/047 G06F17/14 G06N3/08

    摘要: A transformer failure diagnosis method and system based on an integrated deep belief network are provided. The disclosure relates to the fields of electronic circuit engineering and computer vision. The method includes the following: obtaining a plurality of vibration signals of transformers of various types exhibiting different failure types, retrieving a feature of each of the vibration signals, and establishing training data through the retrieved features; training a plurality of deep belief networks exhibiting different learning rates through the training data and obtaining a failure diagnosis correct rate of each of the deep belief networks; and keeping target deep belief networks corresponding to the failure diagnosis correct rates that satisfy requirements, building an integrated deep belief network through each of the target deep belief networks, and performing a failure diagnosis on the transformers through the integrated deep belief network.

    NUMBER THEORETIC TRANSFORM WITH PARALLEL COEFFICIENT PROCESSING

    公开(公告)号:US20240348441A1

    公开(公告)日:2024-10-17

    申请号:US18132274

    申请日:2023-04-07

    申请人: NXP B.V.

    IPC分类号: H04L9/30 G06F17/14

    CPC分类号: H04L9/3093 G06F17/14

    摘要: Electronic device and method for performing number theoretic transforms (NTTs) on polynomials for cryptography uses an arithmetic transformation on an input polynomial with n coefficients to divide the input polynomial into multiple polynomials each with less than n coefficients such that the coefficients of the multiple polynomials add up to n. An NTT transformation is executed on the multiple polynomials such that the coefficients of each of the multiple polynomials are processed in parallel butterfly operations. A cryptographic operation is performed based on the results of the NTT transformation.

    Methods and apparatus for performing matrix transformations within a memory array

    公开(公告)号:US12118056B2

    公开(公告)日:2024-10-15

    申请号:US16403245

    申请日:2019-05-03

    发明人: Fa-Long Luo

    IPC分类号: G06F17/16 G06F9/30 G06F17/14

    摘要: Methods and apparatus for performing matrix transforms within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform matrix transformations within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one exemplary embodiment, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a vector-matrix product. In some cases, the MMU may additionally perform various other logical operations within the digital domain.

    Sensor based data set method and apparatus

    公开(公告)号:US12093005B2

    公开(公告)日:2024-09-17

    申请号:US17505458

    申请日:2021-10-19

    申请人: Intel Corporation

    摘要: Apparatus and method to facilitate automatic detection of a device state are disclosed herein. Selectively constraining a sensor based data set associated with one or more states of a device, wherein selectively constraining the sensor based data set includes analyzing a distribution of the sensor based data set to determine whether to constrain the sensor based data set, the sensor based data set including a first class and a second class of data values. Determining a threshold associated with the sensor based data set by selecting the threshold based on a variance between the first and second classes of the sensor based data set, wherein selecting the threshold includes using a constrained sensor based data set when the sensor based data set is determined to be constrained, and wherein the threshold indicates the data values associated with the first and second classes.

    Methods and Apparatus for Performing Video Processing Matrix Operations Within a Memory Array

    公开(公告)号:US20240211537A1

    公开(公告)日:2024-06-27

    申请号:US18433974

    申请日:2024-02-06

    发明人: Fa-Long Luo

    摘要: Video processing matrix operations within a memory fabric, including converting a memory array into a matrix fabric for discrete cosine transform (DCT) matrix transformations and performing DCT matrix operations therein. For example, DCT matrix-matrix multiplication operations are performed within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). Matrix-matrix multiplication operations may be obtained using separate matrix-vector products. The matrix fabric may use a crossbar construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a vector-matrix product. In some cases, the MMU may additionally perform various other logical operations within the digital domain.

    Mac processing pipeline having conversion circuitry, and methods of operating same

    公开(公告)号:US12008066B2

    公开(公告)日:2024-06-11

    申请号:US17816487

    申请日:2022-08-01

    IPC分类号: G06F17/14 G06T1/20

    CPC分类号: G06F17/14 G06T1/20

    摘要: An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to process the data, using filter weights, via a plurality of multiply and accumulate operations. The integrated circuit includes first conversion circuitry, coupled the pipeline, having inputs to receive a plurality of sets of data, wherein each set of data includes a plurality of data, Winograd conversion circuitry to convert each set of data to a corresponding Winograd set of data, floating point format conversion circuitry, coupled to the Winograd conversion circuitry, to convert the data of each Winograd set of data to a floating point data format. In operation, the multiplier-accumulator circuits are configured to perform the plurality of multiply and accumulate operations using the data of the plurality of Winograd sets of data from the first conversion circuitry and the filter weights, and generate output data based on the multiply and accumulate operations.