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公开(公告)号：US20240276735A1
公开(公告)日：2024-08-15
申请号：US18448918
申请日：2023-08-12
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H10B53/30 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05541 , H01L2224/05557 , H01L2224/05686 , H01L2224/08145 , H01L2224/80931 , H01L2924/04941 , H01L2924/04953
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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2.发明公开公开(公告)号：US20240276734A1
公开(公告)日：2024-08-15
申请号：US18448917
申请日：2023-08-12
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H10B53/20 , H01L28/55 , H01L28/91 , H01L28/92 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H10B51/20
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US20240274651A1
公开(公告)日：2024-08-15
申请号：US18448852
申请日：2023-08-11
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H01L28/60 , H01L24/32 , H01L28/55 , H01L2224/32145
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US20240257854A1
公开(公告)日：2024-08-01
申请号：US18161808
申请日：2023-01-30
发明人： Rajeev Kumar Dokania , Mustansir Yunus Mukadam , Erik Unterborn , Pramod Kolar , Amrita Mathuriya , Debo Olaosebikan , Tanay Gosavi , Noriyuki Sato , Sasikanth Manipatruni
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2273
摘要： Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.
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公开(公告)号：US12029043B1
公开(公告)日：2024-07-02
申请号：US17552330
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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6.发明公开公开(公告)号：US20240211872A1
公开(公告)日：2024-06-27
申请号：US18358545
申请日：2023-07-25
发明人： Sasikanth Manipatruni , Niloy Mukherjee , Noriyuki Sato , Tanay Gosavi , Somilkumar J. Rathi , James David Clarkson , Rajeev Kumar Dokania , Debo Olaosebikan , Amrita Mathuriya
CPC分类号： G06Q10/087 , G06Q30/04 , G16C20/70
摘要： A method for monetizing ferroelectric process development is described. In at least one embodiment, the method comprises procuring a target material based on a model driven selection which is based on charge, mass and magnetic moment, and/or mass of the atomic constituents of the target material. The method further comprises applying the target material to a fabrication process to build a ferroelectric device. The method further comprises generating a notification indicative of procurement of the target material and application of the target material. The method further comprises electronically transmitting the notification to a customer, wherein the notification includes an invoice having a line item associated with a cost of the procuring of the target material and application of the target material.
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公开(公告)号：US11955512B1
公开(公告)日：2024-04-09
申请号：US17552266
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H01L21/321 , H01L21/768 , H01L49/02
CPC分类号： H01L28/91 , H01L21/3212 , H01L21/76843 , H01L28/92
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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公开(公告)号：US11955153B1
公开(公告)日：2024-04-09
申请号：US17654908
申请日：2022-03-15
发明人： Rajeev Kumar Dokania , Amrita Mathuriya , Debo Olaosebikan , Tanay Gosavi , Noriyuki Sato , Sasikanth Manipatruni
CPC分类号： G11C11/161 , G11C11/221 , H01L25/0652 , H01L28/55 , H01L28/75 , H10B12/20 , H10B12/48 , H10B53/00
摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
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9.发明授权公开(公告)号：US11903219B1
公开(公告)日：2024-02-13
申请号：US17654526
申请日：2022-03-11
发明人： Rajeev Kumar Dokania , Amrita Mathuriya , Debo Olaosebikan , Tanay Gosavi , Noriyuki Sato , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
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公开(公告)号：US11871584B1
公开(公告)日：2024-01-09
申请号：US17553475
申请日：2021-12-16
发明人： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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