公开(公告)号：US20240347397A1

公开(公告)日：2024-10-17

申请号：US18757370

申请日：2024-06-27

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Niloy Mukherjee ,  Noriyuki Sato ,  Tanay Gosavi ,  Mauricio Manfrini ,  Somilkumar J. Rathi ,  James David Clarkson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Amrita Mathuriya

IPC: H01L21/66 ,  H10B51/30 ,  H10B53/30

CPC classification number: H01L22/20 ,  H10B51/30 ,  H10B53/30

Abstract: A method to deposit a multi-layer stack for device applications includes implementing a model driven target selection for deposition. One or more targets may be procured with an initial stoichiometric composition or elemental purity. The targets may be utilized to form the multi-layer stack, and measurements may be made of chemical composition and electrical properties of the multi-layer stack. The measurements may be compared to reference target values and if measurement results are not within tolerance, the composition of the targets can be changed to yield a successive multi-layer stack. The process can be iterated until measurement results are within tolerance of target results. Additional experimentation with post deposition thermal anneal can be performed to optimize multi-layer stack properties.

公开(公告)号：US12096638B2

公开(公告)日：2024-09-17

申请号：US17654905

申请日：2022-03-15

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  G11C11/22 ,  H10B53/10 ,  H10B61/00 ,  H10B63/00

CPC classification number: H10B53/30 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H10B53/10 ,  H10B61/22 ,  H10B63/30

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

公开(公告)号：US12069866B2

公开(公告)日：2024-08-20

申请号：US17465792

申请日：2021-09-02

Applicant: Kepler Computing, Inc.

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L49/02 ,  H03K19/185 ,  H10B53/10 ,  H10B53/40

CPC classification number: H10B53/30 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H03K19/185 ,  H10B53/10

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US12034086B1

公开(公告)日：2024-07-09

申请号：US17552269

申请日：2021-12-15

Applicant: Kepler Computing Inc.

Inventor： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H01L21/768 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L29/945 ,  H01L21/76834 ,  H01L21/7687 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12010854B1

公开(公告)日：2024-06-11

申请号：US17553480

申请日：2021-12-16

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Niloy Mukherjee ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Somilkumar J. Rathi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H01L21/00 ,  H10B53/30

CPC classification number: H10B53/30

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

公开(公告)号：US11961877B1

公开(公告)日：2024-04-16

申请号：US17550899

申请日：2021-12-14

Applicant: Kepler Computing Inc.

Inventor： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  G11C11/22 ,  H01L49/02

CPC classification number: H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30 ,  G11C11/221

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US11871583B2

公开(公告)日：2024-01-09

申请号：US17478849

申请日：2021-09-17

Applicant: Kepler Computing, Inc.

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H10B53/10 ,  H01L49/02 ,  H03K19/185 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B53/30 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/535 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H03K19/185 ,  H10B53/10

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US11869928B2

公开(公告)日：2024-01-09

申请号：US17550904

申请日：2021-12-14

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Niloy Mukherjee ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Somilkumar J. Rathi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H01L21/00 ,  H01L49/02 ,  H10B53/30 ,  G11C11/22

CPC classification number: H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30 ,  G11C11/221

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

公开(公告)号：US11818897B1

公开(公告)日：2023-11-14

申请号：US17517298

申请日：2021-11-02

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: G11C11/00 ,  H10B53/30

CPC classification number: H10B53/30

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US11785782B1

公开(公告)日：2023-10-10

申请号：US17346094

申请日：2021-06-11

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H10B53/40

CPC classification number: H10B53/40

Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.