公开(公告)号：US12027458B2

公开(公告)日：2024-07-02

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20210098387A1

公开(公告)日：2021-04-01

申请号：US16585666

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Mauro Kobrinsky ,  Richard Vreeland ,  Ramanan Chebiam ,  William Brezinski ,  Brennen Mueller ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

公开(公告)号：US11532558B2

公开(公告)日：2022-12-20

申请号：US16585666

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Mauro Kobrinsky ,  Richard Vreeland ,  Ramanan Chebiam ,  William Brezinski ,  Brennen Mueller ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

公开(公告)号：US11424160B2

公开(公告)日：2022-08-23

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/02

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US20200258778A1

公开(公告)日：2020-08-13

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/02 ,  H01L21/8238

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US11887887B2

公开(公告)日：2024-01-30

申请号：US17850876

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

CPC classification number: H01L21/76801 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/528 ,  H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H04B1/40 ,  H01L2224/08146 ,  H01L2224/80895

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

公开(公告)号：US20220139823A1

公开(公告)日：2022-05-05

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20240304543A1

公开(公告)日：2024-09-12

申请号：US18668038

申请日：2024-05-17

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20240063071A1

公开(公告)日：2024-02-22

申请号：US17891880

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jeffery Bielefeld ,  Adel Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Gauri Auluck ,  Kimin Jun ,  Mohammad Enamul Kabir ,  Nagatoshi Tsunoda ,  Renata Camillo-Castillo ,  Tristan A. Tronic ,  Xavier Brun

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L25/0655 ,  H01L24/08 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.

公开(公告)号：US20210098360A1

公开(公告)日：2021-04-01

申请号：US16586279

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.