公开(公告)号：US20240355730A1

公开(公告)日：2024-10-24

申请号：US18761397

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC分类号： H01L23/522 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5228 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L28/24

摘要： Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US12119378B2

公开(公告)日：2024-10-15

申请号：US17121073

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-Heng Wang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/225 ,  H01L21/268 ,  H01L21/311 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/02236 ,  H01L21/2253 ,  H01L21/268 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

公开(公告)号：US20240297236A1

公开(公告)日：2024-09-05

申请号：US18648069

申请日：2024-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

摘要： A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US12057488B2

公开(公告)日：2024-08-06

申请号：US17850393

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

摘要： A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US20240250139A1

公开(公告)日：2024-07-25

申请号：US18438575

申请日：2024-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42364 ,  H01L21/28026 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

公开(公告)号：US20240096999A1

公开(公告)日：2024-03-21

申请号：US18520326

申请日：2023-11-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US11855169B2

公开(公告)日：2023-12-26

申请号：US17826673

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC分类号： H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US20220384244A1

公开(公告)日：2022-12-01

申请号：US17815975

申请日：2022-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pang-Sheng Chang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Li-Chieh Wu ,  Chun-Wei Hsu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

公开(公告)号：US11508822B2

公开(公告)日：2022-11-22

申请号：US16899140

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC分类号： H01L29/04 ,  H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

摘要： A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

公开(公告)号：US20220359399A1

公开(公告)日：2022-11-10

申请号：US17874804

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC分类号： H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48

摘要： Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.