- 专利标题： METHODS OF REDUCING CAPACITANCE IN FIELD-EFFECT TRANSISTORS
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申请号： US18648069申请日： 2024-04-26
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公开(公告)号： US20240297236A1公开(公告)日： 2024-09-05
- 发明人: Chun-Han Chen , Chen-Ming Lee , Fu-Kai Yang , Mei-Yun Wang
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 分案原申请号： US16587474 2019.09.30
- 主分类号： H01L29/51
- IPC分类号： H01L29/51 ; H01L21/02 ; H01L21/3105 ; H01L29/40 ; H01L29/78
摘要：
A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
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