公开(公告)号：US20230197594A1

公开(公告)日：2023-06-22

申请号：US17559483

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L. Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Eric J.M. Moret ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58

CPC classification number: H01L23/49827 ,  H05K3/32 ,  H05K1/181 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/5384 ,  H01R12/58 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

公开(公告)号：US10109940B2

公开(公告)日：2018-10-23

申请号：US15377254

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： Thomas A. Boyd ,  Feifei Cheng ,  Donald T. Tran ,  Russell S. Aoki ,  Karumbu Meyyappan

IPC: H01R12/70 ,  H01R12/88

Abstract: Embodiments herein relate to port frames and connectors for direct connections to integrated circuit packages. In various embodiments, a port frame to receive a connector and maintain a connection between the connector and a computer processor package may include a protrusion to provide stable attachment of the port frame to a bolster frame, a first wall, a second wall opposite the first wall, a first detent in the first wall, and a second detent in the second wall where the connector is to be received between the first wall and the second wall, and where the first detent is to receive a first locking protrusion extending from the connector and the second detent is to receive a second locking protrusion extending from the connector. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197621A1

公开(公告)日：2023-06-22

申请号：US17559365

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L. Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Eric J.M. Moret ,  Pooya Tadayon

IPC: H01L23/538 ,  H01L23/498 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58

CPC classification number: H01L23/5384 ,  H01L23/49827 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01R12/58

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.

公开(公告)号：US10044115B2

公开(公告)日：2018-08-07

申请号：US14757626

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Donald T. Tran ,  Gregorio Murtagian ,  Kuang Liu ,  Srikant Nekkanty ,  Feroz Mohammad ,  Karumbu Meyyappan ,  Hong Xie ,  Russell S. Aoki ,  Gaurav Chawla

IPC: H01R4/50 ,  H01R13/639 ,  H01R4/52 ,  H01R13/508 ,  H01R12/85 ,  H01R12/72

Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.

公开(公告)号：US20230185037A1

公开(公告)日：2023-06-15

申请号：US17548167

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Eric J. M. Moret ,  Pooya Tadayon ,  Karumbu Meyyappan ,  Paul J. Diglio

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/4269 ,  G02B6/4284

Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.

公开(公告)号：US11543454B2

公开(公告)日：2023-01-03

申请号：US16141422

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Pooya Tadayon ,  Karumbu Meyyappan

IPC: G01R31/319 ,  G01R1/073

Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

公开(公告)号：US11622466B2

公开(公告)日：2023-04-04

申请号：US16902048

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Kyle Arrington ,  David Craig ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K7/14 ,  H05K7/20 ,  H01L23/22

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20200096567A1

公开(公告)日：2020-03-26

申请号：US16141422

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Pooya Tadayon ,  Karumbu Meyyappan

IPC: G01R31/319 ,  G01R1/073

Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

公开(公告)号：US20170187134A1

公开(公告)日：2017-06-29

申请号：US14757915

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Thomas A. Boyd ,  Jeffory L. Smalley ,  Russell S. Aoki ,  Karumbu Meyyappan

IPC: H01R12/72 ,  H01R43/26 ,  H01R13/635 ,  H01R13/648 ,  H01R12/70 ,  H01R13/631

CPC classification number: H01R12/721 ,  H01R12/7005 ,  H01R12/774 ,  H01R13/508 ,  H01R13/631 ,  H01R13/635 ,  H01R13/6485 ,  H01R43/26

Abstract: An example apparatus for connecting linear edge cards includes a housing to hold at least one set of conductive contacts facing perpendicularly towards a mating plane. The apparatus further includes an activator bar coupled to the housing, the activator bar to hold two parts of the housing apart via two opposing normal forces. The apparatus also includes a contact load spring coupled to the housing, the contact load spring to apply two forces parallel to the direction of the conductive contacts and against the two opposing normal forces of the activator bar. The apparatus further includes an ejector spring coupled to the contact load spring and the activator bar. The ejector spring is to apply a force perpendicular to the two opposing normal forces of the activator bar and in a direction of an opening of the housing.

公开(公告)号：US20240297119A1

公开(公告)日：2024-09-05

申请号：US18573116

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Karumbu Meyyappan ,  Andres Ramirez Macias ,  Zhe Chen ,  Jeffory L. Smalley ,  Zhichao Zhang ,  Steven A. Klein ,  Eric Erike

IPC: H01L23/532 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/32 ,  H01L23/4093 ,  H01L23/49811 ,  H01L23/5283

Abstract: An electronic device (100, 800, 1000) and associated methods are disclosed. In one example, the electronic device (100, 800, 1000) includes an interconnect socket (102, 302, 402, 802, 1004, 1320, 1402, 1506) that includes a liquid metal. In selected examples, the interconnect socket (102, 302, 402) includes a resilient material spacer (130, 230, 330, 430) located between pins (110, 210, 310, 410) in an array of pins (110, 210, 310, 410). In selected examples, the electronic device (1000) includes configurations to aid in de-socketing.