公开(公告)号：US20230253312A1

公开(公告)日：2023-08-10

申请号：US18301447

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/7685 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US11631639B2

公开(公告)日：2023-04-18

申请号：US17671394

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/00

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US11532547B2

公开(公告)日：2022-12-20

申请号：US16547732

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Tsai ,  Ming-Han Lee ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.

公开(公告)号：US20220165661A1

公开(公告)日：2022-05-26

申请号：US17671394

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US11251118B2

公开(公告)日：2022-02-15

申请号：US16572683

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/48 ,  H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US20210082804A1

公开(公告)日：2021-03-18

申请号：US16572683

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US20210057333A1

公开(公告)日：2021-02-25

申请号：US16547732

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Tsai ,  Ming-Han Lee ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.

公开(公告)号：US08901007B2

公开(公告)日：2014-12-02

申请号：US13733222

申请日：2013-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Sunil Kumar Singh ,  Tien-I Bao

IPC: H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76813

Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

Abstract translation: 本公开涉及一种制造半导体结构的方法，其中在半导体衬底上形成低k电介质层。 通过用由CO 2，CO或含羧基的源气体和含氟源气体的混合物形成的等离子体蚀刻等离子体蚀刻，可以在低k电介质层附近形成特征。 该方法允许形成镶嵌结构，而不会遇到与低K电介质层的损坏相关的问题。

公开(公告)号：US20140187044A1

公开(公告)日：2014-07-03

申请号：US13733222

申请日：2013-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Sunil Kumar Singh ,  Tien-I Bao

IPC: H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/76811 ,  H01L21/76813

Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

Abstract translation: 本公开涉及一种制造半导体结构的方法，其中在半导体衬底上形成低k电介质层。 通过用由CO 2，CO或含羧基的源气体和含氟源气体的混合物形成的等离子体蚀刻等离子体蚀刻，可以在低k电介质层附近形成特征。 该方法允许形成镶嵌结构，而不会遇到与低K电介质层的损坏相关的问题。

公开(公告)号：US20240339396A1

公开(公告)日：2024-10-10

申请号：US18745773

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/32 ,  H01L24/37 ,  H01L2924/181

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.