公开(公告)号：US12087693B2

公开(公告)日：2024-09-10

申请号：US17441217

申请日：2019-05-09

Applicant: Intel NDTM US LLC

Inventor： Daniel R. Lamborn ,  Chuan Sun ,  Qi Zhou

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H10B41/50 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76895 ,  H01L23/5283 ,  H10B43/50 ,  H10B41/50 ,  H10B43/27

Abstract: Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes.