公开(公告)号：US20220093316A1

公开(公告)日：2022-03-24

申请号：US17029870

申请日：2020-09-23

申请人： Intel Corporation

发明人： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC分类号： H01F27/28 ,  H01L23/64 ,  H01F41/32 ,  H01L23/498

摘要： An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

申请人： Intel Corporation

发明人： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/485 ,  H01L23/49827

摘要： An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

申请人： Intel Corporation

发明人： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC分类号： H01L23/498 ,  H01L21/48

摘要： An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

申请人： Intel Corporation

发明人： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC分类号： H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

摘要： Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

申请人： Intel Corporation

发明人： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC分类号： H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

摘要： Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US20240006380A1

公开(公告)日：2024-01-04

申请号：US17856830

申请日：2022-07-01

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rahul Manepalli ,  Marcel Wall ,  Darko Grujicic

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L25/0655 ,  H01L23/5383 ,  H01L23/49866 ,  H01L21/4857

摘要： High-density IC die package routing structures with one or more nitrided surfaces. Metallization features may be formed, for example with a plating process. Following the plating process, a surface of the metallization features may be exposed to a surface treatment that incorporates nitrogen onto a surface of the metallization. The presence of nitrogen may chemically improve adhesion between finely patterned metallization features and package dielectric material. Accordingly, surface roughness of metallization features may be reduced without suffering delamination. With lower surface roughness, metallization features may transmit higher frequency data signals with lower insertion loss.

公开(公告)号：US20240331921A1

公开(公告)日：2024-10-03

申请号：US18739049

申请日：2024-06-10

申请人： Intel Corporation

发明人： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC分类号： H01F27/28 ,  H01F41/32 ,  H01L23/498 ,  H01L23/64

CPC分类号： H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

摘要： An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20240321657A1

公开(公告)日：2024-09-26

申请号：US18189782

申请日：2023-03-24

申请人： Intel Corporation

发明人： Darko Grujicic ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rengarajan Shanmugam ,  Marcel Wall ,  Sashi Kandanur ,  Rahul Manepalli ,  Robert May

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L23/49827 ,  H01L23/49866 ,  G02B6/4214

摘要： Photonic integrated circuit packages and methods of manufacturing are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.

公开(公告)号：US20240006300A1

公开(公告)日：2024-01-04

申请号：US17855667

申请日：2022-06-30

申请人： Intel Corporation

发明人： Yi Yang ,  Srinivas Pietambaram ,  Darko Grujicic ,  Marcel Wall ,  Suddhasattwa Nad ,  Ala Omer ,  Brian P. Balch ,  Wei Wei

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49894 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/4857 ,  H01L21/4864

摘要： Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example package assembly includes a substrate, a dielectric layer and a conductive layer between the substrate and the dielectric layer. The conductive layer has a surface roughness of less than 1 micrometer (μm). A film is provided between the dielectric layer and the conductive layer, and between exposed surfaces of the substrate adjacent the conductive layer and the dielectric layer. The film including silicon and nitrogen and being substantially free of hydrogen.

公开(公告)号：US20220293509A1

公开(公告)日：2022-09-15

申请号：US17197531

申请日：2021-03-10

申请人： Intel Corporation

发明人： Rahul Manepalli ,  Suddhasattwa Nad ,  Marcel Wall ,  Darko Grujicic

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48

摘要： An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.