公开(公告)号：US20230097624A1

公开(公告)日：2023-03-30

申请号：US17484486

申请日：2021-09-24

申请人： Intel Corporation

发明人： Kyle McElhinny ,  Onur Ozkan ,  Ali Lehaf ,  Xiaoying Guo ,  Steve Cho ,  Leonel Arana ,  Jung Kyu Han ,  Srinivas Pietambaram ,  Sashi Kandanur ,  Alexander Aguinaga

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/12 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50

摘要： Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

申请人： Intel Corporation

发明人： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC分类号： H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

摘要： Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US20240321657A1

公开(公告)日：2024-09-26

申请号：US18189782

申请日：2023-03-24

申请人： Intel Corporation

发明人： Darko Grujicic ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Rengarajan Shanmugam ,  Marcel Wall ,  Sashi Kandanur ,  Rahul Manepalli ,  Robert May

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L23/49827 ,  H01L23/49866 ,  G02B6/4214

摘要： Photonic integrated circuit packages and methods of manufacturing are disclosed. An example integrated circuit package includes: a semiconductor die; a package substrate supporting the semiconductor die, the package substrate including a glass core, the glass core including a through glass via extending between opposing first and second surfaces of the glass core, the glass core including a recess spaced apart from the through glass via, the recess defined by a third surface of the glass core, the recess having a different shape than the through glass via; and a reflective metal disposed on the third surface to define a mirror, the reflective metal also disposed between a wall of the through glass via and a conductive material disposed in the through glass via.

公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

申请人： Intel Corporation

发明人： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC分类号： B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC分类号： B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

摘要： MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

申请人： Intel Corporation

发明人： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

摘要： Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11488918B2

公开(公告)日：2022-11-01

申请号：US16177022

申请日：2018-10-31

申请人： Intel Corporation

发明人： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

摘要： Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).