公开(公告)号：US11508525B2

公开(公告)日：2022-11-22

申请号：US16819404

申请日：2020-03-16

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuhito Higuchi ,  Susumu Obata ,  Keiichiro Matsuo ,  Mitsuo Sano

IPC: H01G4/33 ,  H01L49/02

Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20170076982A1

公开(公告)日：2017-03-16

申请号：US15050683

申请日：2016-02-23

Applicant: Kabushiki Kaisha Toshiba

Inventor： Seiya Sakakura ,  Masamune Takano ,  Yusaku Asano ,  Keiichiro Matsuo

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/56 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/568 ,  H01L21/67051 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54453

Abstract: Provided is a device manufacturing method according to an embodiment including forming a film on a second plane side of a substrate having a first plane and the second plane, forming grooves on the substrate from the first plane side so that the film remains, and performing an ultrasonic process on the substrate in a liquid to remove the film of the second plane side at positions where the grooves are formed.

Abstract translation: 本发明提供一种根据实施例的器件制造方法，包括在具有第一平面和第二平面的衬底的第二平面侧上形成膜，从第一平面侧在衬底上形成凹槽，使得膜保持，并且执行 在液体中的基板上进行超声波处理，以在形成凹槽的位置处移除第二平面侧的膜。

公开(公告)号：US12107023B2

公开(公告)日：2024-10-01

申请号：US17473196

申请日：2021-09-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiichiro Matsuo ,  Izuru Komatsu ,  Haruka Yamamoto

IPC: H01L23/053 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/492

CPC classification number: H01L23/053 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48177

Abstract: A power module includes a base plate, a casing, a substrate unit, a terminal plate, a first resin layer, and a second resin layer. The substrate unit includes a substrate fixed on the base plate, a dam part, a semiconductor chip, a metal member, and a wire. The dam part is formed along an edge of the substrate. The wire includes an electrode plate connection portion, and a chip connection portion. The first resin layer is located inward of the dam part. The chip connection portion and the electrode plate connection portion are located inside the first resin layer. The second resin layer is located on the first resin layer. The upper surface of the metal member is located inside the second resin layer. An elastic modulus of the second resin layer is less than that of the first resin layer.

公开(公告)号：US11551864B2

公开(公告)日：2023-01-10

申请号：US17181033

申请日：2021-02-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Keiichiro Matsuo ,  Susumu Obata ,  Mitsuo Sano ,  Kazuhito Higuchi ,  Kazuo Shimokawa

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/84 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49 ,  H01L29/92 ,  H01L29/417 ,  H01L29/786 ,  H01G4/005 ,  H01G4/38 ,  H01G4/228 ,  H05K1/18

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

公开(公告)号：US10978358B2

公开(公告)日：2021-04-13

申请号：US16531718

申请日：2019-08-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mitsuo Sano ,  Keiichiro Matsuo ,  Susumu Obata ,  Kazuhito Higuchi ,  Kazuo Shimokawa

IPC: H01L21/306 ,  H01L21/66 ,  G01N23/223

Abstract: According to one embodiment, in a processing system and determining method, a X-ray intensity of character X-rays generated by irradiating a catalytic layer of a noble metal formed on a surface of a substrate with X-rays is detected. In the processing system and the determining method, either the detected X-ray intensity or a parameter calculated using the X-ray intensity is obtained as a determination parameter. In the processing system and the determining method, based at least on the determination parameter, whether or not the catalytic layer has been formed into a state suitable for etching the surface of the substrate is determined.

公开(公告)号：US11410914B2

公开(公告)日：2022-08-09

申请号：US16926008

申请日：2020-07-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiichiro Matsuo ,  Jun Karasawa ,  Haruka Yamamoto ,  Shinya Hayashiyama

IPC: H01L23/492 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31

Abstract: A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.

公开(公告)号：US10964474B2

公开(公告)日：2021-03-30

申请号：US16742095

申请日：2020-01-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiichiro Matsuo ,  Susumu Obata ,  Mitsuo Sano ,  Kazuhito Higuchi ,  Kazuo Shimokawa

IPC: H01G4/01 ,  H01G4/008 ,  H01G4/30 ,  H01G4/40 ,  H01L21/02 ,  H01L21/20 ,  H01L21/311 ,  H01L29/00 ,  H01L29/92 ,  H01L29/94 ,  H01L49/02 ,  H01G4/005 ,  H01G4/228 ,  H05K1/18 ,  H01G4/38

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

公开(公告)号：US10854466B2

公开(公告)日：2020-12-01

申请号：US16267456

申请日：2019-02-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiichiro Matsuo ,  Susumu Obata ,  Mitsuo Sano ,  Kazuhito Higuchi ,  Kazuo Shimokawa

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/033

Abstract: An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.

公开(公告)号：US20200098582A1

公开(公告)日：2020-03-26

申请号：US16359427

申请日：2019-03-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mitsuo SANO ,  Keiichiro Matsuo ,  Susumu Obata ,  Kazuhito Higuchi ,  Kazuo Shimokawa

IPC: H01L21/306 ,  H01L21/308

Abstract: According to an embodiment, a method of forming a porous layer includes forming a porous layer containing a noble metal on a surface made of a semiconductor by displacement plating. The plating solution used in the displacement plating contains a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential. The noble metal source produces an ion containing the noble metal in water. The plating solution has a pH value in a range of 1 to 6.

公开(公告)号：US12131966B2

公开(公告)日：2024-10-29

申请号：US17467839

申请日：2021-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Kioxia Corporation

Inventor： Fuyuma Ito ,  Yasuhito Yoshimizu ,  Nobuhito Kuge ,  Yui Kagi ,  Susumu Obata ,  Keiichiro Matsuo ,  Mitsuo Sano

IPC: H01L21/66 ,  C30B25/18 ,  H01L21/02 ,  H10B43/27

CPC classification number: H01L22/30 ,  C30B25/186 ,  H01L21/02002 ,  H01L21/02005 ,  H01L22/34 ,  H10B43/27

Abstract: A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.