公开(公告)号：US20240290750A1

公开(公告)日：2024-08-29

申请号：US18367506

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun LEE ,  Hyunggil BAEK ,  Su-Chang LEE ,  Gyunghwan OH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19041

Abstract: A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.