公开(公告)号：US12096549B1

公开(公告)日：2024-09-17

申请号：US17582734

申请日：2022-01-24

Applicant: Vicor Corporation

Inventor： Patrizio Vinciarelli ,  Patrick R. Lavery ,  Rudolph F. Mutter ,  Jeffery J. Kirk ,  Andrew T. D'Amico

IPC: H05K1/02 ,  H01L23/053 ,  H01L23/057 ,  H01L23/28 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/16 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24 ,  H05K3/38 ,  H01L21/44 ,  H01L23/14

CPC classification number: H05K1/0204 ,  H05K1/111 ,  H05K1/181 ,  H05K1/186 ,  H05K3/0014 ,  H05K3/0026 ,  H05K3/0044 ,  H05K3/0079 ,  H05K3/16 ,  H05K3/18 ,  H05K3/207 ,  H05K3/24 ,  H05K3/381 ,  H01L21/44 ,  H01L23/053 ,  H01L23/057 ,  H01L23/147 ,  H01L23/28 ,  H05K2201/1003 ,  Y10T29/49146

Abstract: Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

公开(公告)号：US11324107B1

公开(公告)日：2022-05-03

申请号：US16705585

申请日：2019-12-06

Applicant: Vicor Corporation

Inventor： Patrizio Vinciarelli ,  Patrick R. Lavery ,  Rudolph F. Mutter ,  Jeffery J. Kirk ,  Andrew T. D'Amico

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/24 ,  H05K3/38 ,  H05K3/18 ,  H05K3/16 ,  H05K3/20 ,  H05K1/11 ,  H01L21/44 ,  H01L23/28 ,  H01L23/14 ,  H01L23/057 ,  H01L23/053

Abstract: Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.