公开(公告)号：US08624316B2

公开(公告)日：2014-01-07

申请号：US13227882

申请日：2011-09-08

申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

公开(公告)号：US20130249102A1

公开(公告)日：2013-09-26

申请号：US13607695

申请日：2012-09-08

申请人： Shinichi NAKAO ,  Ichiro Mizushima

发明人： Shinichi NAKAO ,  Ichiro Mizushima

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a plurality of wires wherein at least some of the regions between wires (inter-wire regions) contain an air gap region formed by capping the wires and inter-wire regions with an insulator film using a film coating process, for example chemical vapor deposition. The existence, size, and shape of the air gap depend upon the film coating parameters and the spacing between wires.

摘要翻译： 一种具有多条导线的半导体器件，其中线（线间区域）中的至少一些区域包含通过使用膜涂覆工艺用绝缘膜覆盖电线和线间区域形成的气隙区域，例如 化学气相沉积。 气隙的存在，尺寸和形状取决于膜涂层参数和电线之间的间距。

公开(公告)号：US08536699B2

公开(公告)日：2013-09-17

申请号：US13272426

申请日：2011-10-13

申请人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

发明人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

IPC分类号： H01L23/34

CPC分类号： C23C16/0272 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  Y10S438/905

摘要： In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.

摘要翻译： 在通过在制造装置的反应室中的基板上形成结构膜的半导体装置的制造工序中，进行反应室内的清洗。 也就是说，在反应室的内壁上沉积由含硼的氮化硅膜制成的预涂膜，在反应室中的基板上形成不含硼的氮化硅膜作为结构膜，内壁 的反应室被干蚀刻以进行清洁。 此时，在从反应室排出的气体中检测到硼后，干法蚀刻终止。

公开(公告)号：US08476708B2

公开(公告)日：2013-07-02

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US08455346B2

公开(公告)日：2013-06-04

申请号：US13075658

申请日：2011-03-30

申请人： Yasuhiro Nojiri ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Yasuhiro Nojiri ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/4763 ,  G11C11/00

CPC分类号： H01L51/0591 ,  B82Y10/00 ,  B82Y40/00 ,  G11C13/0002 ,  G11C13/025 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.

摘要翻译： 根据一个实施例，公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 此外，该方法可以包括在第二电极膜上形成第二互连。

公开(公告)号：US08415242B2

公开(公告)日：2013-04-09

申请号：US12886135

申请日：2010-09-20

申请人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

发明人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

IPC分类号： H01L21/3205

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

公开(公告)号：US20120031331A1

公开(公告)日：2012-02-09

申请号：US13272426

申请日：2011-10-13

申请人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

发明人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

IPC分类号： H01L21/66 ,  B05C11/00 ,  C23C16/455

CPC分类号： C23C16/0272 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  Y10S438/905

摘要： In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.

摘要翻译： 在通过在制造装置的反应室中的基板上形成结构膜的半导体装置的制造工序中，进行反应室内的清洗。 也就是说，在反应室的内壁上沉积由含硼的氮化硅膜制成的预涂膜，在反应室中的基板上形成不含硼的氮化硅膜作为结构膜，内壁 的反应室被干蚀刻以进行清洁。 此时，在从反应室排出的气体中检测到硼后，干法蚀刻终止。

公开(公告)号：US20110233646A1

公开(公告)日：2011-09-29

申请号：US12886135

申请日：2010-09-20

申请人： Ichiro MIZUSHIMA ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

发明人： Ichiro MIZUSHIMA ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

摘要翻译： 根据一个实施例，提供了一种非易失性半导体存储器件，其中通过在柱状半导体膜的高度方向上经由电荷存储层提供在柱状半导体膜的侧面上具有栅电极膜的多个晶体管形成的存储器串， 基本上垂直地以矩阵形式布置在基底上。 提供了一种由半导体材料制成的耦合部分，其连接形成在预定方向上彼此相邻的一对存储器串的柱状半导体膜的下部。 每个柱状半导体膜由大致单晶状锗膜或硅锗膜形成。

公开(公告)号：US20110108905A1

公开(公告)日：2011-05-12

申请号：US13007258

申请日：2011-01-14

申请人： Masayuki ICHIGE ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki ICHIGE ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US20090152623A1

公开(公告)日：2009-06-18

申请号：US12335701

申请日：2008-12-16

申请人： Masakazu GOTO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Kimitoshi OKANO ,  Satoshi INABA ,  Ichiro MIZUSHIMA

发明人： Masakazu GOTO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Kimitoshi OKANO ,  Satoshi INABA ,  Ichiro MIZUSHIMA

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/7845

摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

摘要翻译： 翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。