公开(公告)号：US08624316B2

公开(公告)日：2014-01-07

申请号：US13227882

申请日：2011-09-08

申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

公开(公告)号：US08476708B2

公开(公告)日：2013-07-02

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US08415242B2

公开(公告)日：2013-04-09

申请号：US12886135

申请日：2010-09-20

申请人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

发明人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

IPC分类号： H01L21/3205

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

公开(公告)号：US20120241841A1

公开(公告)日：2012-09-27

申请号：US13227882

申请日：2011-09-08

申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

公开(公告)号：US20120181602A1

公开(公告)日：2012-07-19

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US08551871B2

公开(公告)日：2013-10-08

申请号：US13240662

申请日：2011-09-22

申请人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

发明人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由 的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中， 从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。

公开(公告)号：US20120090535A1

公开(公告)日：2012-04-19

申请号：US13240662

申请日：2011-09-22

申请人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

发明人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

IPC分类号： C30B25/02

CPC分类号： H01L21/02636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由 的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中， 从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。

公开(公告)号：US08043945B2

公开(公告)日：2011-10-25

申请号：US12401453

申请日：2009-03-10

申请人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

发明人： Ichiro Mizushima ,  Shinji Mori ,  Masahiko Murano ,  Tsutomu Sato ,  Takashi Nakao ,  Hiroshi Itokawa

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由 的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中， 从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。

公开(公告)号：US08012858B2

公开(公告)日：2011-09-06

申请号：US12560265

申请日：2009-09-15

申请人： Masahiko Murano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Shinji Mori ,  Shuji Katsui ,  Hiroshi Itokawa

发明人： Masahiko Murano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Shinji Mori ,  Shuji Katsui ,  Hiroshi Itokawa

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02378 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.

摘要翻译： 根据一个实施例的制造半导体器件的方法包括：在氢气气氛中，在压力为第一压力和温度为的条件下，除去天然氧化物膜并将硅氮化物粘附在Si基衬底的区域上 第一温度，在所述Si基衬底上形成含氮化硅的构件，所述区域是未被构件覆盖的区域; 将温度从第一温度降低到第二温度，同时保持在氢气气氛中的第一压力下的压力; 将压力从第一压力降低到第二压力，同时将温度保持在第二温度在氢气气氛中; 并且在所述压力降低到所述第二压力之后，在前驱体气体气氛中，在所述Si基基板的区域上外延生长晶体，所述晶体包括Si和Ge中的至少一种，所述前体气体气体包括氢， Si和Ge。

公开(公告)号：US20100167482A1

公开(公告)日：2010-07-01

申请号：US12646097

申请日：2009-12-23

申请人： Shinji MORI ,  Masahiko Murano ,  Ichiro Mizushima

发明人： Shinji MORI ,  Masahiko Murano ,  Ichiro Mizushima

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823857

摘要： There is provided a method of manufacturing a semiconductor device that allows the threshold voltage of a p-type MOSFET to be controlled with accuracy as high as possible in a multi-oxide process.The method forms two types of field-effect transistors including gate insulating films having different film thickness in a first region and a second region on a silicon substrate, respectively, and includes forming a silicon-germanium film (Si1-xGex, 0

摘要翻译： 提供了一种制造半导体器件的方法，其允许在多氧化物工艺中以尽可能高的精度来控制p型MOSFET的阈值电压。 该方法分别形成两种类型的场效应晶体管，其包括在第一区域中具有不同膜厚度的栅极绝缘膜和硅衬底上的第二区域，并且包括形成硅 - 锗膜（Si1-xGex，0