公开(公告)号：US08637915B2

公开(公告)日：2014-01-28

申请号：US13007258

申请日：2011-01-14

Applicant: Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

Inventor： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract translation: 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：USRE44630E1

公开(公告)日：2013-12-10

申请号：US13616208

申请日：2012-09-14

Applicant: Tetsuya Kai ,  Ryuji Ohba ,  Yoshio Ozawa

Inventor： Tetsuya Kai ,  Ryuji Ohba ,  Yoshio Ozawa

IPC: H01L21/331

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.

Abstract translation: 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在所述半导体衬底的表面上的隧道绝缘膜，所述隧道绝缘膜包括半导体晶粒，所述半导体晶粒包括在 隧道绝缘膜的两端部比隧道绝缘膜的其他部分所包含的半导体晶粒小的晶粒尺寸，隧道绝缘膜上设置的电荷存储层，设置在电荷存储层上的绝缘膜，以及控制 栅电极设置在绝缘膜上。

公开(公告)号：US08604536B2

公开(公告)日：2013-12-10

申请号：US12406841

申请日：2009-03-18

Applicant: Katsuyuki Sekine ,  Yoshio Ozawa

Inventor： Katsuyuki Sekine ,  Yoshio Ozawa

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.

Abstract translation: 半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极 设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜 以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

公开(公告)号：US08324679B2

公开(公告)日：2012-12-04

申请号：US13430153

申请日：2012-03-26

Applicant: Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

Inventor： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract translation: 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US20120282773A1

公开(公告)日：2012-11-08

申请号：US13487280

申请日：2012-06-04

Applicant: Isao Kamioka ,  Junichi Shiozawa ,  Ryu Kato ,  Yoshio Ozawa

Inventor： Isao Kamioka ,  Junichi Shiozawa ,  Ryu Kato ,  Yoshio Ozawa

IPC: H01L21/302

CPC classification number: H01L29/7881 ,  H01L21/76208 ,  H01L27/11521 ,  H01L29/66825

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.

Abstract translation: 在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成其上表面和侧表面被暴露的导电膜和上表面暴露的绝缘膜。 该方法还包括通过施加微波，射频波或电子回旋共振等将由等离子体产生的等离子体中包含的氧化离子或氮化离子供应到导电膜的暴露侧表面和绝缘膜的暴露的上表面 对半导体衬底施加预定的电压，从而进行导电膜的暴露的侧表面和绝缘膜的暴露的上表面的各向异性氧化或各向异性氮化。

公开(公告)号：US08304352B2

公开(公告)日：2012-11-06

申请号：US13051031

申请日：2011-03-18

Applicant: Masayuki Tanaka ,  Kazuhiro Matsuo ,  Yoshio Ozawa

Inventor： Masayuki Tanaka ,  Kazuhiro Matsuo ,  Yoshio Ozawa

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11582

Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.

Abstract translation: 根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜 并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分 半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

公开(公告)号：US20120273863A1

公开(公告)日：2012-11-01

申请号：US13546074

申请日：2012-07-11

Applicant: Yoshio OZAWA ,  Fumiki AlSO

Inventor： Yoshio OZAWA ,  Fumiki AlSO

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11578 ,  H01L21/8221 ,  H01L27/11568 ,  H01L27/11582

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract translation: 非易失性半导体存储器件包括：半导体部件; 记录膜，设置在所述半导体构件的表面上并能够存储电荷; 以及设置在所述存储膜上的多个控制栅电极，彼此间​​隔开并且沿着与所述表面平行的方向布置。 插入在一个控制栅电极之间的材料和位于与控制栅电极相邻的控制栅电极正下方的部分的平均介电常数低于介于一个控制栅之间的材料的平均介电常数 电极和位于一个控制栅电极正下方的半导体部件的一部分。

公开(公告)号：US08198159B2

公开(公告)日：2012-06-12

申请号：US12054089

申请日：2008-03-24

Applicant: Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

Inventor： Masayuki Tanaka ,  Yoshio Ozawa ,  Hirokazu Ishida ,  Katsuaki Natori ,  Seiji Inumiya

IPC: H01L21/324 ,  H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

Abstract translation: 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。

公开(公告)号：US20120094476A1

公开(公告)日：2012-04-19

申请号：US13051031

申请日：2011-03-18

Applicant: Masayuki TANAKA ,  Kazuhiro Matsuo ,  Yoshio Ozawa

Inventor： Masayuki TANAKA ,  Kazuhiro Matsuo ,  Yoshio Ozawa

IPC: H01L21/28

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11582

Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.

Abstract translation: 根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜 并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分 半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

公开(公告)号：US20110248329A1

公开(公告)日：2011-10-13

申请号：US13164946

申请日：2011-06-21

Applicant: Toshitake Yaegashi ,  Yoshio Ozawa

Inventor： Toshitake Yaegashi ,  Yoshio Ozawa

IPC: H01L27/105 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.

Abstract translation: 半导体集成电路器件包括：第一，第二栅电极，第一，第二扩散层，电连接到第一扩散层的接触电极;第一绝缘膜，其在第一和第二栅电极之间具有凹入部分，并且不含氮作为 主要成分，形成在第一绝缘膜上并且不含氮作为主要成分的第二绝缘膜和形成在第一扩散层上的第三绝缘膜，第一栅电极，第二扩散层和第二栅电极， 第二绝缘膜设置在部分区域之间。 形成第二绝缘膜以填充凹部，并且第一和第二栅电极之间的部分具有至少包含第一绝缘膜和第二绝缘膜的多层结构。