公开(公告)号：US20240055313A1

公开(公告)日：2024-02-15

申请号：US18494198

申请日：2023-10-25

Applicant: Texas Instruments Incorporated

Inventor： Michael Todd Wyant ,  Matthew John Sherbin ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  You Chye How

IPC: H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3185 ,  H01L23/3171 ,  H01L23/552 ,  H01L21/568 ,  H01L21/78 ,  H01L21/561 ,  H01L2221/68336 ,  H01L21/6836

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US20210210440A1

公开(公告)日：2021-07-08

申请号：US16737237

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

IPC: H01L23/58 ,  H01L23/532 ,  H01L23/528

Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

公开(公告)号：US12009319B2

公开(公告)日：2024-06-11

申请号：US16737237

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

IPC: H01L23/58 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/585 ,  H01L23/528 ,  H01L23/53209

Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

公开(公告)号：US11855024B2

公开(公告)日：2023-12-26

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao Chen ,  Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  Jonathan Andrew Montoya ,  Salvatore Frank Pavone

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L24/25 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/09181 ,  H01L2224/2541 ,  H01L2224/73209 ,  H01L2224/81801

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US11410947B2

公开(公告)日：2022-08-09

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

公开(公告)号：US20240332119A1

公开(公告)日：2024-10-03

申请号：US18740444

申请日：2024-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US11984418B2

公开(公告)日：2024-05-14

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03502 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11848 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13647 ,  H01L2924/0132

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

公开(公告)号：US20230317673A1

公开(公告)日：2023-10-05

申请号：US17710941

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Vivek Swaminathan Sridharan ,  Rajen Manicon Murugan ,  Patrick Francis Thompson

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L24/24 ,  H01L24/16 ,  H01L24/20 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/73209 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2924/37001 ,  H01L2924/186 ,  H01L2924/182 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/17134

Abstract: A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.

公开(公告)号：US20230187306A1

公开(公告)日：2023-06-15

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L25/0655 ,  H01L24/48 ,  H01L21/4882 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US12009280B2

公开(公告)日：2024-06-11

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.