公开(公告)号：US12237219B2

公开(公告)日：2025-02-25

申请号：US17038947

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US11443996B2

公开(公告)日：2022-09-13

申请号：US15909679

申请日：2018-03-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

公开(公告)号：US11362020B2

公开(公告)日：2022-06-14

申请号：US17098930

申请日：2020-11-16

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Jonathan Andrew Montoya ,  Jovenic Romero Esquejo ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/50 ,  H01L21/768 ,  H01L23/31 ,  H01L21/60

Abstract: A semiconductor package includes an IC having circuitry configured for at least one function with some nodes connected to bond pads, with first metal posts on the bond pads, and dome support metal posts configured in a ring having a top rim defining an inner cavity with solder on the top rim and extending over an area of the inner cavity for providing a solder dome that covers the inner cavity to provide a covered air cavity over a portion of the circuitry. A leadframe includes a plurality of leads or lead terminals. The IC is flipchip attached with a solder connection to the leadframe so that the first metal posts are attached to the leads or the lead terminals. A mold compound provides encapsulation for the semiconductor package except on at least a bottom side of the leads or lead terminals.

公开(公告)号：US11127515B2

公开(公告)日：2021-09-21

申请号：US16854839

申请日：2020-04-21

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01B13/00 ,  H01B1/02

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

公开(公告)号：US12068221B2

公开(公告)日：2024-08-20

申请号：US16985103

申请日：2020-08-04

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/373 ,  C23C14/16 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/3736 ,  C23C14/165 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/78

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

公开(公告)号：US20240153903A1

公开(公告)日：2024-05-09

申请号：US18414125

申请日：2024-01-16

Applicant: Texas Instruments Incorporated

Inventor： Katleen Fajardo Timbol ,  Salvatore Frank Pavone ,  Rafael Jose Lizares Guevara

IPC: H01L23/00 ,  H01L21/027

CPC classification number: H01L24/13 ,  H01L21/027 ,  H01L24/04 ,  H01L24/11 ,  H01L2221/1068 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2924/177

Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.

公开(公告)号：US11587858B2

公开(公告)日：2023-02-21

申请号：US17323939

申请日：2021-05-18

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  B23K1/00 ,  C25D5/12 ,  C25D5/18 ,  C25D7/12 ,  C25D3/22 ,  B23K101/36 ,  C25D3/12

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US10796956B2

公开(公告)日：2020-10-06

申请号：US16022956

申请日：2018-06-29

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US10692830B2

公开(公告)日：2020-06-23

申请号：US16038598

申请日：2018-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00

Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1

公开(公告)号：US20190109062A1

公开(公告)日：2019-04-11

申请号：US15909679

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.