Invention Grant
- Patent Title: Wafer chip scale packages with visible solder fillets
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Application No.: US17463047Application Date: 2021-08-31
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Publication No.: US11855024B2Publication Date: 2023-12-26
- Inventor: Qiao Chen , Vivek Swaminathan Sridharan , Christopher Daniel Manack , Patrick Francis Thompson , Jonathan Andrew Montoya , Salvatore Frank Pavone
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn Jos; Frank D. Cimino
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.
Public/Granted literature
- US20230065075A1 WAFER CHIP SCALE PACKAGES WITH VISIBLE SOLDER FILLETS Public/Granted day:2023-03-02
Information query
IPC分类: