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公开(公告)号:US20170221842A1
公开(公告)日:2017-08-03
申请号:US15420815
申请日:2017-01-31
Applicant: Infineon Technologies AG
Inventor: Roman ROTH , Frank HILLE , Hans-Joachim SCHULZE
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L24/49 , H01L2224/02181 , H01L2224/0219 , H01L2224/03462 , H01L2224/0347 , H01L2224/03848 , H01L2224/04042 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0566 , H01L2224/05664 , H01L2224/0603 , H01L2224/48091 , H01L2224/491 , H01L2224/4911 , H01L2924/00014 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2224/45099
Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
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公开(公告)号:US20180366428A1
公开(公告)日:2018-12-20
申请号:US16059468
申请日:2018-08-09
Applicant: Infineon Technologies AG
Inventor: Roman ROTH , Frank HILLE , Hans-Joachim SCHULZE
IPC: H01L23/00
Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.
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