公开(公告)号：US20140332939A1

公开(公告)日：2014-11-13

申请号：US14341772

申请日：2014-07-26

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理用餐。

公开(公告)号：US20140370661A1

公开(公告)日：2014-12-18

申请号：US14474420

申请日：2014-09-02

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US20110175217A1

公开(公告)日：2011-07-21

申请号：US12730230

申请日：2010-03-24

Applicant: Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

Inventor： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

IPC: H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/73 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Abstract translation: 本技术涉及通过将多个管芯电耦合到上引线框架和下引线框架而封装的半导体。 上引线框架中的每个相应引线组的相对边缘弯曲。 上引线框架中的引线电耦合在相应管芯上的相应触头和下引线框架中引线的相应下部。 上引线框架的每个相应的引线组的弯曲的相对边缘在封装之前支撑上引线框架，以在封装半导体中实现上引脚和下引线框架的引线之间的多个管芯的期望位置。 在封装的芯片被分离之后，上部引线具有L形并且在芯片的上侧上电耦合管芯触头，以在芯片的下侧引出引线，使得封装触点位于半导体封装的同一侧。

公开(公告)号：US09184152B2

公开(公告)日：2015-11-10

申请号：US14341772

申请日：2014-07-26

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L29/72 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US08822273B2

公开(公告)日：2014-09-02

申请号：US13229667

申请日：2011-09-09

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L29/72

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US08586419B2

公开(公告)日：2013-11-19

申请号：US12730230

申请日：2010-03-24

Applicant: Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

Inventor： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

IPC: H01L21/00

CPC classification number: H01L24/73 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Abstract translation: 本技术涉及通过将多个管芯电耦合到上引线框架和下引线框架而封装的半导体。 上引线框架中的每个相应引线组的相对边缘弯曲。 上引线框架中的引线电耦合在相应管芯上的相应触头和下引线框架中引线的相应下部。 上引线框架的每个相应的引线组的弯曲的相对边缘在封装之前支撑上引线框架，以在封装半导体中实现上引脚和下引线框架的引线之间的多个管芯的期望位置。 在封装的芯片被分离之后，上部引线具有L形并且在芯片的上侧上电耦合管芯触头，以在芯片的下侧引出引线，使得封装触点位于半导体封装的同一侧。

公开(公告)号：US20120112331A1

公开(公告)日：2012-05-10

申请号：US13229667

申请日：2011-09-09

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US09595503B2

公开(公告)日：2017-03-14

申请号：US14474420

申请日：2014-09-02

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US09093359B2

公开(公告)日：2015-07-28

申请号：US11479619

申请日：2006-06-30

Applicant: King Owyang ,  Mohammed Kasem ,  Yuming Bai ,  Frank Kuo ,  Sen Mao ,  Sam Kuo

Inventor： King Owyang ,  Mohammed Kasem ,  Yuming Bai ,  Frank Kuo ,  Sen Mao ,  Sam Kuo

IPC: H05K1/11 ,  H05K1/14 ,  H01L25/16 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00 ,  H02M3/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/20 ,  H05K3/28 ,  H05K3/34

CPC classification number: G05F3/08 ,  H01L23/36 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H02M3/00 ,  H02M3/04 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/141 ,  H05K1/181 ,  H05K3/202 ,  H05K3/284 ,  H05K3/3436 ,  H05K7/20409 ,  H05K7/205 ,  H05K2201/10166 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Abstract translation: 在单个表面贴装封装中实现的完整的电源管理系统。 该系统可被绘制到DC-DC转换器系统，并且在无引线表面贴装封装中包括驱动器/控制器，MOSFET晶体管，无源元件（例如，电感器，电容器，电阻器）和可选的二极管。 在各种实施例中，MOSFET晶体管可以由绝缘栅双极晶体管，IGBT替代。 该系统还可以是电源管理系统，智能电源模块或运动控制系统。 无源组件可以连接在引线框连接之间。 可以使用金属夹接合技术将有源部件耦合到引线框架。 在一个实施例中，暴露的金属底部可以用作有效散热器。

公开(公告)号：US20060108671A1

公开(公告)日：2006-05-25

申请号：US10996148

申请日：2004-11-23

Applicant: Mohammed Kasem ,  King Owyang ,  Frank Kuo ,  Serge Jaunay ,  Sen Mao ,  Oscar Ou ,  Peter Wang ,  Chang-Sheng Chen

Inventor： Mohammed Kasem ,  King Owyang ,  Frank Kuo ,  Serge Jaunay ,  Sen Mao ,  Oscar Ou ,  Peter Wang ,  Chang-Sheng Chen

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Abstract translation: 半导体封装包括在上引线框架和下引线框架之间插入倒装芯片的管芯。 下引线框架具有与芯片底表面上的端子对准的触点。 上引线框架接触管芯顶部的端子，并且上引线框架的边缘围绕模具的边缘向下弯曲，使上引线框架成杯形。 上引线框架的边缘接触下引线框架的另一部分，使得封装的所有触点是共面的，并且可以表面安装在印刷电路板上。 芯片的端子通过焊料层电连接到引线框架。 预定了将管芯与引线框架连接的各个焊料层的厚度，以通过许多热循环来优化封装的性能。 这是通过用多个台面制造下引线框架并使用双重回流焊工艺来完成的。