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    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250006696A1

    公开(公告)日：2025-01-02

    申请号：US18525724

    申请日：2023-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongkoon LEE ,  Youngchan KO ,  Byung Ho KIM

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00

    Abstract: A semiconductor package may include a first redistribution layer, bridge dies on an upper surface of the first redistribution layer, a second redistribution layer on the bridge dies and electrically connected to the bridge dies, conductive posts between the first and second redistribution layer, and semiconductor chips on an upper surface of the second redistribution layer. Each bridge die may include connection pads on an upper surface of the bridge dies. A pitch between first connection pads of a first bridge die among the bridge dies may be smaller than a pitch between second connection pads of a second bridge die among the bridge dies. A distance between an upper surface of the first bridge die and a lower surface of the second redistribution layer may be smaller than a distance between an upper surface of the second bridge die and a lower surface of the second redistribution layer.

    SEMICONDUCTOR PACKAGES HAVING WIRING PATTERNS
    4.
    发明申请
    SEMICONDUCTOR PACKAGES HAVING WIRING PATTERNS 有权

    公开(公告)号：US20230131240A1

    公开(公告)日：2023-04-27

    申请号：US17723689

    申请日：2022-04-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngchan KO ,  Myungsam Kang ,  Jeongseok Kim ,  Bongju Cho

    IPC: H01L23/538 ,  H01L25/10 ,  H01L23/498

    Abstract: A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer; a semiconductor chip on the lower redistribution structure; wiring patterns disposed on the lower redistribution structure and extending in a horizontal direction, the wiring patterns including a first wiring pattern; metal patterns on the wiring patterns, the metal patterns including a first connection pillar and a first dummy pillar disposed on the first wiring pattern; an encapsulant on the lower redistribution structure, the semiconductor chip, the wiring patterns, and the metal patterns; and an upper redistribution structure on the encapsulant. The first connection pillar is directly connected to the upper redistribution structure.

    FAN-OUT TYPE SEMICONDUCTOR PACKAGE
    5.
    发明申请
    FAN-OUT TYPE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220068784A1

    公开(公告)日：2022-03-03

    申请号：US17218356

    申请日：2021-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Bongju CHO

    IPC: H01L23/498 ,  H01L23/552 ,  H01L25/10

    Abstract: A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 μm, and the side shielding pattern has a width of no less than about 5 μm.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240421034A1

    公开(公告)日：2024-12-19

    申请号：US18403936

    申请日：2024-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungho KIM ,  Youngchan KO ,  Gyeongho KIM ,  Yongkoon LEE ,  Myungdo CHO

    IPC: H01L23/42 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

    Abstract: A semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210265251A1

    公开(公告)日：2021-08-26

    申请号：US17031141

    申请日：2020-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyungdon MUN ,  Myungsam KANG ,  Youngchan KO ,  Yieok KWON ,  Jeongseok KIM ,  Gongje LEE ,  Bongju CHO

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 μm or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210210414A1

    公开(公告)日：2021-07-08

    申请号：US17012294

    申请日：2020-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam KANG ,  Youngchan KO ,  Kyungdon MUN

    IPC: H01L23/485 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

    Abstract: A semiconductor package includes a redistribution substrate having a first redistribution layer, a semiconductor chip on the redistribution substrate and connected to the first redistribution layer, a vertical connection conductor on the redistribution substrate and electrically connected to the semiconductor chip through the first redistribution layer, a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor, and an encapsulant covering at least a portion of each of the semiconductor chip, the vertical connection conductor, and the core member, the encapsulant filling the first and second through-holes, wherein the vertical connection conductor has a cross-sectional shape with a side surface tapered to have a width of a lower surface thereof is narrower than a width of an upper surface thereof, and the first and second through-holes have a cross-sectional shape tapered in a direction opposite to the vertical connection conductor.

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