公开(公告)号：US12278191B2

公开(公告)日：2025-04-15

申请号：US17723689

申请日：2022-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngchan Ko ,  Myungsam Kang ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer; a semiconductor chip on the lower redistribution structure; wiring patterns disposed on the lower redistribution structure and extending in a horizontal direction, the wiring patterns including a first wiring pattern; metal patterns on the wiring patterns, the metal patterns including a first connection pillar and a first dummy pillar disposed on the first wiring pattern; an encapsulant on the lower redistribution structure, the semiconductor chip, the wiring patterns, and the metal patterns; and an upper redistribution structure on the encapsulant. The first connection pillar is directly connected to the upper redistribution structure.

公开(公告)号：US12261105B2

公开(公告)日：2025-03-25

申请号：US18098158

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun ,  Bongju Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US20240347468A1

公开(公告)日：2024-10-17

申请号：US18754434

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

公开(公告)号：US20240321755A1

公开(公告)日：2024-09-26

申请号：US18391844

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang

IPC: H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/5381 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: Provided is a semiconductor package capable of minimizing the size of a silicon (Si) interposer and minimizing warpage of a package substrate while maintaining a chip-to-chip connection function. The semiconductor package includes a package substrate including a glass core substrate, a silicon (Si) bridge interposer, and a multi-layer wiring layer disposed under the glass core substrate and the Si bridge interposer, and at least two semiconductor devices stacked on the package substrate, wherein a cavity is formed in a central portion of the glass core substrate, and the Si bridge interposer is embedded in the cavity.

公开(公告)号：US11784129B2

公开(公告)日：2023-10-10

申请号：US17183562

申请日：2021-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Taesung Jeong

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214

Abstract: A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

公开(公告)号：US20230178492A1

公开(公告)日：2023-06-08

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/08 ,  H01L23/5385 ,  H01L2224/08235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US11569175B2

公开(公告)日：2023-01-31

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20220068822A1

公开(公告)日：2022-03-03

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US12046562B2

公开(公告)日：2024-07-23

申请号：US18151517

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

公开(公告)号：US12002798B2

公开(公告)日：2024-06-04

申请号：US17861359

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Yongjin Park

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06548

Abstract: A fan-out type semiconductor package may include a frame, an upper chip stack, a first redistribution pattern, a lower chip stack, a second redistribution pattern and a redistribution post. The frame may have a cavity. The upper chip stack may be arranged in the cavity. The first redistribution pattern may be arranged under the frame. The first redistribution pattern may be electrically connected with the upper chip stack. The lower chip stack may be arranged under the first redistribution pattern. The second redistribution pattern may be arranged under the lower chip stack. The second redistribution pattern may be electrically connected with the lower chip stack. The redistribution post may be electrically connected between the first redistribution pattern and the second redistribution pattern. Thus, the fan-out type semiconductor package may have an improved heat dissipation characteristic with a thin thickness.