知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.018 seconds)

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11916002B2

    公开(公告)日：2024-02-27

    申请号：US17551938

    申请日：2021-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun

    IPC: H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

    CPC classification number: H01L23/49822 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08235

    Abstract: Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

    Semiconductor package and method of manufacturing the semiconductor package
    4.
    发明授权
    Semiconductor package and method of manufacturing the semiconductor package 有权

    公开(公告)号：US12159826B2

    公开(公告)日：2024-12-03

    申请号：US17476670

    申请日：2021-09-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

    IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package includes a support substrate having connection wirings disposed therein. At least one capacitor is disposed on the support substrate. The capacitor has first and second electrodes that are exposed from an upper surface of the support substrate. A redistribution wiring layer covers the upper surface of the support substrate. The redistribution wiring layer has redistribution wirings electrically connected to the connection wirings and the first and second electrodes respectively. A semiconductor chip is disposed on the redistribution wiring layer. The semiconductor chip has chip pads that are electrically connected to the redistribution wirings and outer connectors disposed on a lower surface of the support substrate and electrically connected to the connection wirings.

    Semiconductor package with under-bump metal structure
    7.
    发明授权
    Semiconductor package with under-bump metal structure 有权

    公开(公告)号：US11581284B2

    公开(公告)日：2023-02-14

    申请号：US17203372

    申请日：2021-03-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

    Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.

    Semiconductor package
    8.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11569158B2

    公开(公告)日：2023-01-31

    申请号：US17228784

    申请日：2021-04-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun ,  Bongju Cho

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

    Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

    SEMICONDUCTOR PACKAGE
    10.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240321728A1

    公开(公告)日：2024-09-26

    申请号：US18733705

    申请日：2024-06-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

    IPC: H01L23/522 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/14

    Abstract: A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

Patent Agency Ranking