公开(公告)号：US20230268265A1

公开(公告)日：2023-08-24

申请号：US18060226

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gongje Lee ,  Sangkyu Lee

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L25/105 ,  H01L23/49833 ,  H01L23/49822 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1094 ,  H01L23/49816

Abstract: A semiconductor package according to an example embodiment of the disclosure includes a first redistribution layer including a first via, a first redistribution pattern, and a first insulating layer, a first semiconductor chip connected to the first redistribution layer via a chip connection terminal, a lower post directly connected to the first redistribution layer, an upper post connected to an upper surface of the lower post, a first mold layer at least partially covering the first redistribution layer, the first semiconductor chip, the lower post, and the upper post, and a second redistribution layer on the upper post and the first mold layer. The upper post has a width that gradually increases as the upper post extends from the lower post toward the second redistribution layer. An upper surface of the upper post is coplanar with an upper surface of the first mold layer.

公开(公告)号：US20240222284A1

公开(公告)日：2024-07-04

申请号：US18228278

申请日：2023-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongju Cho ,  Jingu Kim ,  Yieok Kwon ,  Wooyoung Kim ,  Gongje Lee ,  Sangkyu Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L23/5386 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/46 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/05024 ,  H01L2224/13008 ,  H01L2224/46

Abstract: Semiconductor package includes lower redistribution layer providing first redistribution wirings and having first region and second region surrounding the first region, semiconductor chip disposed on the first region and electrically connected to the first redistribution wirings, sealing member covering the semiconductor chip on the lower redistribution layer, plurality of vertical conductive structures penetrating the sealing member on the second region and electrically connected to the first redistribution wirings, upper redistribution layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures and plurality of bonding pads. The vertical conductive structures are bonded to the bonding pad and extend vertically from the plurality of bonding pads. The vertical conductive structure includes first to third conductive pillar portions sequentially stacked. The first conductive pillar portion has first length and the third conductive pillar portion has third length greater than the first length.

公开(公告)号：US12119305B2

公开(公告)日：2024-10-15

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08235 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20230178492A1

公开(公告)日：2023-06-08

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/08 ,  H01L23/5385 ,  H01L2224/08235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US11569175B2

公开(公告)日：2023-01-31

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20220068822A1

公开(公告)日：2022-03-03

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.