公开(公告)号：US20240258276A1

公开(公告)日：2024-08-01

申请号：US18446844

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Kim ,  Sangkyu Lee ,  Jingu Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81

Abstract: A semiconductor package may include: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs; a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure; a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure and the printed circuit board; and a back side redistribution layer on the molding material.

公开(公告)号：US11726613B2

公开(公告)日：2023-08-15

申请号：US17427774

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Kim ,  Daehyun Jo

IPC: G06F3/041 ,  G06F21/32 ,  G09G3/20

CPC classification number: G06F3/0418 ,  G06F21/32 ,  G09G3/2096 ,  G09G2360/144

Abstract: An electronic device and a method for operating the electronic device are provided. The electronic device includes a housing which includes a first surface and a second surface facing the first surface, a display which is disposed on at least a part of the first surface, a proximity sensor which is disposed between the display and the second surface, an illuminance sensor, and a processor which is operably connected to the display and the illuminance sensor, wherein the processor is configured to activate the display and the illuminance sensor in response to the occurrence of an event, measure, by using the illuminance sensor, illuminance of a region where the electronic device is disposed, confirm the characteristic of an input occurring on the display by an external object, and determine, based on the measured illuminance and the characteristic of the input, whether or not to inactivate a touch input reception function of at least a partial region of the display.

公开(公告)号：US20240222284A1

公开(公告)日：2024-07-04

申请号：US18228278

申请日：2023-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongju Cho ,  Jingu Kim ,  Yieok Kwon ,  Wooyoung Kim ,  Gongje Lee ,  Sangkyu Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L23/5386 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/46 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/05024 ,  H01L2224/13008 ,  H01L2224/46

Abstract: Semiconductor package includes lower redistribution layer providing first redistribution wirings and having first region and second region surrounding the first region, semiconductor chip disposed on the first region and electrically connected to the first redistribution wirings, sealing member covering the semiconductor chip on the lower redistribution layer, plurality of vertical conductive structures penetrating the sealing member on the second region and electrically connected to the first redistribution wirings, upper redistribution layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures and plurality of bonding pads. The vertical conductive structures are bonded to the bonding pad and extend vertically from the plurality of bonding pads. The vertical conductive structure includes first to third conductive pillar portions sequentially stacked. The first conductive pillar portion has first length and the third conductive pillar portion has third length greater than the first length.

公开(公告)号：US20240321805A1

公开(公告)日：2024-09-26

申请号：US18405791

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungho Hahn ,  Wooyoung Kim ,  Minwoo Rhee ,  Bumki Moon ,  Kyeongbin Lim

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L2224/27614 ,  H01L2224/27616 ,  H01L2224/27848 ,  H01L2924/1434

Abstract: A method of manufacturing a semiconductor device includes preparing a first substrate and a second substrate respectively including a bonding layer having metal pads and a dielectric layer, performing a planarization process on a surface of the bonding layer of each of the first and second substrates, applying wet atomic layer etching to the surface of the bonding layer so that a surface of the metal pad is recessed to a target depth, and bonding the bonding layer of the first substrate to the bonding layer of the second substrate using an annealing process.

公开(公告)号：US20240213113A1

公开(公告)日：2024-06-27

申请号：US18343011

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Eok Kwon ,  Wooyoung Kim ,  Jingu Kim ,  Sangkyu Lee

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/3675 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes: a first redistribution layer; at least one lower die on the first redistribution layer; a first through-via on the first redistribution layer; a first molding material that molds the first redistribution layer, the at least one lower die, and the first through-via; a second redistribution layer on the at least one lower die, the first through-via, and the first molding material; at least one upper die on the second redistribution layer and having a thickness between 1.2 and 1.7 times, including endpoints, greater than a thickness of the at least one lower die; a second through-via on the second redistribution layer; a second molding material that molds the second redistribution layer, the at least one upper die, and the second through-via; and a heat dissipation member on the at least one upper die and the second through-via, wherein the heat dissipation member contacts the second through-via.