公开(公告)号：US20230092242A1

公开(公告)日：2023-03-23

申请号：US17507010

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Gang DUAN

IPC: H01L23/15 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20220197044A1

公开(公告)日：2022-06-23

申请号：US17131714

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kaveh HOSSEINI ,  Conor O'KEEFFE ,  Brandon C. MARIN ,  Hiroki TANAKA

IPC: G02B27/28 ,  G02B6/10 ,  F21V8/00 ,  G02B6/27

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a dual polarization chiplet that may be used by an optical receiver to split multi-polarized light traveling on a single fiber and carrying two or more light signals into two or more fibers each carrying the particular light signal. The dual polarization chiplet may also be used by an optical transmitter to combine multiple light signals to be transmitted onto a single fiber, where each of the multiple light signals are represented by a different polarization of a wavelength on the single fiber. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20220187549A1

公开(公告)日：2022-06-16

申请号：US17122352

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Brandon C. MARIN ,  Kristof DARMAWKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Srinivas V. PIETAMBARAM

IPC: G02B6/42

Abstract: Embodiments disclosed herein include photonics package with Faraday rotators to improve efficiency. In an embodiment, a photonics package comprises a package substrate and a compute die over the package substrate. In an embodiment, the photonics package further comprises a photonics die over the package substrate. In an embodiment, the compute die is communicatively coupled to the photonics die by a bridge in the package substrate. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the package substrate, and a Faraday rotator passing through the IHS and optically coupled to the photonics die.

公开(公告)号：US20200258800A1

公开(公告)日：2020-08-13

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy ECTON ,  Oscar OJEDA ,  Leonel ARANA ,  Suddhasattwa NAD ,  Robert MAY ,  Hiroki TANAKA ,  Brandon C. MARIN

IPC: H01L23/31 ,  H05K1/02 ,  H05K3/06 ,  H01L21/283

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20190206767A1

公开(公告)日：2019-07-04

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

CPC classification number: H01L23/485 ,  H01L21/0275 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54426 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02372

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20240243066A1

公开(公告)日：2024-07-18

申请号：US18622511

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20240105580A1

公开(公告)日：2024-03-28

申请号：US17953213

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Kyle MCELHINNY ,  Hiroki TANAKA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15

CPC classification number: H01L23/49866 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a core, and a pad over the core. In an embodiment, a shell is around the core, and a surface finish is over the shell. In an embodiment, the electronic package further comprises a solder resist over the pad, where an opening is formed through the solder resist to expose the surface finish.

公开(公告)号：US20240097079A1

公开(公告)日：2024-03-21

申请号：US17949857

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Khaled AHMED ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Paul WEST ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L25/0753 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.