公开(公告)号：US20210125908A1

公开(公告)日：2021-04-29

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20180076123A1

公开(公告)日：2018-03-15

申请号：US15603859

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/48 ,  H01L25/10 ,  H01L21/66

CPC classification number: H01L22/32 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/18 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

公开(公告)号：US20230317590A1

公开(公告)日：2023-10-05

申请号：US18096861

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/544 ,  H10B80/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/544 ,  H10B80/00 ,  H01L21/4857 ,  H01L24/20 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/16 ,  H01L2224/16227 ,  H01L23/49822 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/13 ,  H01L2224/13147 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2224/211 ,  H01L24/48 ,  H01L2224/48228 ,  H01L2224/48105 ,  H01L2224/48091

Abstract: A semiconductor package is provided. The semiconductor package includes: a first redistribution substrate; a semiconductor chip provided on the first redistribution substrate; a molding layer provided on the first redistribution substrate and the semiconductor chip; and a second redistribution substrate provided on the molding layer. The second redistribution substrate includes: redistribution patterns spaced apart from one another; a first dummy conductive pattern spaced apart from the redistribution patterns; an insulating layer provided on the first dummy conductive pattern; and a marking metal layer provided on the insulating layer and spaced apart from the first dummy conductive pattern. Sidewalls of the marking metal layer overlap the first dummy conductive pattern along a vertical direction perpendicular to an upper surface of the first redistribution substrate.

公开(公告)号：US20230046098A1

公开(公告)日：2023-02-16

申请号：US17680815

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Eungkyu KIM ,  Inhyung SONG ,  Hyeonseok LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/34

Abstract: A semiconductor package includes a package substrate, a semiconductor stack on the package substrate, a passive device on the package substrate and spaced apart from the semiconductor stack, and a stiffener on the package substrate and extending around an outer side of the semiconductor stack. The stiffener includes a first step surface extends over the passive device. A width of a bottom surface of the stiffener is smaller than a width of a top surface of the stiffener.

公开(公告)号：US20220336375A1

公开(公告)日：2022-10-20

申请号：US17853181

申请日：2022-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/367

Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

公开(公告)号：US20200185314A1

公开(公告)日：2020-06-11

申请号：US16447441

申请日：2019-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/498 ,  H01L21/48

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

公开(公告)号：US20240203850A1

公开(公告)日：2024-06-20

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20240055344A1

公开(公告)日：2024-02-15

申请号：US18483884

申请日：2023-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49816 ,  H01L21/4857 ,  H05K1/11 ,  H05K1/111 ,  H05K1/182 ,  H01L24/16

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

公开(公告)号：US20230148218A1

公开(公告)日：2023-05-11

申请号：US18153601

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16227

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20220336338A1

公开(公告)日：2022-10-20

申请号：US17857696

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.