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    ELECTRONIC DEVICE AND CONTROLLING METHOD OF ELECTRONIC DEVICE
    2.
    发明公开
    ELECTRONIC DEVICE AND CONTROLLING METHOD OF ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240346312A1

    公开(公告)日：2024-10-17

    申请号：US18750655

    申请日：2024-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jijoong MOON ,  Parichay KAPOOR ,  Jihoon LEE ,  Hyeonseok LEE ,  Myungjoo HAM

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04

    Abstract: An electronic apparatus may include a memory configured to store data related to a neural network model and at least one processor configured to divide a learning step performed through a plurality of layers of the neural network model into a plurality of steps including a forward propagation step, a gradient calculation step, and a derivative calculation step, and determine an execution order of the plurality of steps, obtain first information regarding in which step of a plurality of steps according to the determined execution order a plurality of sensors used in the plurality of layers are used, based on the determined execution order, integrate the determined execution order based on the first information and second information regarding whether tensors used in neighboring layers from among the plurality of layers are able to be shared, allocate the data to the plurality of tensors by minimizing a region of the memory for allocating data corresponding to the plurality of tensors, based on the integrated execution order, and train the neural network model according to the integrated execution order using the plurality of tensors and the data allocated to the plurality of tensors. Various other embodiments are possible to be implemented.

    SEMICONDUCTOR PACKAGE
    7.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240038642A1

    公开(公告)日：2024-02-01

    申请号：US18121429

    申请日：2023-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongkyu Kim ,  Joonsung KIM ,  Hyeonseok LEE ,  Hyeonjeong HWANG

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

    CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

    Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230069490A1

    公开(公告)日：2023-03-02

    申请号：US17723981

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonseok LEE ,  Jongyoun KIM ,  Seokhyun LEE

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220310496A1

    公开(公告)日：2022-09-29

    申请号：US17509224

    申请日：2021-10-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

    Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

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