公开(公告)号：US20240203961A1

公开(公告)日：2024-06-20

申请号：US18226180

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim SUK ,  Inhyung SONG

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/32 ,  H01L25/162 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/16227 ,  H01L2224/32265 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19106

Abstract: A semiconductor package may include a first redistribution substrate, a semiconductor chip disposed on the first redistribution substrate, a mold layer covering the semiconductor chip and including a first opening exposing a portion of a top surface of the semiconductor chip, a first passive device disposed on the portion of the top surface of the semiconductor chip exposed by the first opening, an insulating pattern filling the first opening and covering at least a portion of the first passive device, and a second redistribution substrate disposed on the mold layer. The first passive device may be spaced apart from the mold layer, with the insulating pattern interposed therebetween.

公开(公告)号：US20240194641A1

公开(公告)日：2024-06-13

申请号：US18348011

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi Woo LEE ,  Hyeonjeong HWANG ,  Mi Hyae PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3157 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08155 ,  H01L2224/16227

Abstract: Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip that are mounted on the substrate, and a bridge chip between a first lateral surface of the first semiconductor chip and a second lateral surface of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are electrically connected through the bridge chip. The first semiconductor chip includes a first chip pad on the first lateral surface. The bridge chip includes a first connection pad on a first surface of the bridge chip. The first lateral surface of the first semiconductor chip and the first surface of the bridge chip are in contact with each other. The first chip pad and the first connection pad include a same material and are bonded to each other to constitute an integral piece formed.

公开(公告)号：US20250046691A1

公开(公告)日：2025-02-06

申请号：US18544707

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Kyung Don MUN ,  Sangjin BAEK ,  Hyeonjeong HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first redistribution line structure; a first semiconductor chip on one surface of the first redistribution line structure; a first conductive bump between, and connecting, the first redistribution line structure and the first semiconductor chip; a first encapsulant encapsulating at least a portion of the first semiconductor chip; a second semiconductor chip on another, opposite surface of the first redistribution line and including a through via; a second conductive bump between, and connecting, the first redistribution line structure and the second semiconductor chip; a second encapsulant encapsulating at least a portion of the second semiconductor chip; and a second redistribution line structure on the second encapsulant. The second encapsulant covers at least a portion of a surface of the second semiconductor chip facing the second redistribution line structure.

公开(公告)号：US20220328388A1

公开(公告)日：2022-10-13

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Kyounglim SUK ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US20240355798A1

公开(公告)日：2024-10-24

申请号：US18500581

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Kyung Don MUN ,  Kyoung Lim SUK

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L28/10 ,  H10B80/00

Abstract: A semiconductor package including a first semiconductor structure on a first redistribution layer structure; first conductive posts on the first redistribution layer structure and next to the first side of the first semiconductor structure; second conductive posts on the first redistribution layer structure and next to a second side opposite to the first side of the first semiconductor structure; a molding material molding the first semiconductor structure, the first conductive posts, and the second conductive posts on the first redistribution layer structure; a second redistribution layer structure on the molding material; a second semiconductor structure on the second redistribution layer structure; a heat dissipation structure on the second redistribution layer structure; and a 3D solenoid inductor including some of the second conductive posts, the redistribution lines at the uppermost of the first redistribution layer structure, and the redistribution lines at the lowermost of the second redistribution layer structure.

公开(公告)号：US20240145375A1

公开(公告)日：2024-05-02

申请号：US18311405

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Dongkyu KIM ,  Inhyung SONG

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/02164 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2225/1041 ,  H01L2924/182

Abstract: A semiconductor package includes an interposer including a first redistribution layer and a second redistribution layer that is on the first redistribution layer and is electrically coupled to the first redistribution layer; and a semiconductor chip on the interposer. The first redistribution layer includes a first organic insulating layer and a plurality of first conductors in the first organic insulating layer. The second redistribution layer includes a second organic insulating layer, a first silicon insulating layer on the second organic insulating layer, and a plurality of second conductors penetrating through both the second organic insulating layer and the first silicon insulating layer. The semiconductor chip includes a second silicon insulating layer and a plurality of third conductors in the second silicon insulating layer. The second conductors are directly bonded to separate, respective third conductors and the first silicon insulating layer is directly bonded to the second silicon insulating layer.

公开(公告)号：US20240120286A1

公开(公告)日：2024-04-11

申请号：US18371152

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonseok LEE ,  Eungkyu KIM ,  Jongyoun KIM ,  Hyeonjeong HWANG

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/105 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16227

Abstract: Provided is a semiconductor package including a lower redistribution structure, an internal semiconductor chip on an upper surface of the lower redistribution structure, an upper redistribution structure electrically connected to the lower redistribution structure through a conductive post, and a molding layer between the upper redistribution structure and the lower redistribution structure, the molding layer being adjacent to the internal semiconductor chip, wherein the upper redistribution structure includes an insulating layer including a redistribution pattern and a first material configured to transmit light, and a fiducial mark formed of the first material, and a lower surface of the fiducial mark is in contact with an upper surface of the molding layer.

公开(公告)号：US20240065003A1

公开(公告)日：2024-02-22

申请号：US18295324

申请日：2023-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu KIM ,  Kyounglim SUK ,  Hyeonseok LEE ,  Hyeonjeong HWANG

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31

CPC classification number: H10B80/00 ,  H01L23/5226 ,  H01L24/16 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/16145 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13155 ,  H01L2224/1318 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13171 ,  H01L2224/13111 ,  H01L2224/13166 ,  H01L2224/1146

Abstract: A semiconductor package includes a memory chip having chip pads on a first surface thereof. A redistribution layer is formed on the first surface of the memory chip. The redistribution layer is electrically connected to the chip pads. The redistribution layer has first redistribution pads on a first surface of the redistribution layer in a first region and a plurality of second redistribution pads on the first surface of the redistribution layer in a second region thereof. A processor chip is disposed on the first region of the redistribution layer and is electrically connected to the first redistribution pads. A sealing member is disposed on the first surface of the redistribution layer and covers the processor chip. Conductive structures are on the second region and penetrate through the sealing member and extend upwardly in a vertical direction away from the second redistribution pads.

公开(公告)号：US20240145396A1

公开(公告)日：2024-05-02

申请号：US18381711

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehoon JANG ,  Hyeonjeong HWANG ,  Kyounglim SUK

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes a base substrate. An interposer substrate includes a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer. The plurality of interposer redistribution structures includes a plurality of conductive interposer patterns and a plurality of conductive interposer vias. A semiconductor chip is disposed between the base substrate and the interposer substrate and is attached on the base substrate. A plurality of conductive connection pads is respectively disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures. The interposer insulation layer includes a plurality of pad holes exposing at least a portion of each of an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns.

公开(公告)号：US20240047324A1

公开(公告)日：2024-02-08

申请号：US18183699

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Dongwook KIM ,  Kyounglim SUK ,  Inhyung SONG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L24/73 ,  H01L24/05 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2225/1058 ,  H01L2224/05008

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.