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    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
    2.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20200098716A1

    公开(公告)日：2020-03-26

    申请号：US16698117

    申请日：2019-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youn Ji MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

    IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

    Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

    SEMICONDUCTOR PACKAGE
    3.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240355798A1

    公开(公告)日：2024-10-24

    申请号：US18500581

    申请日：2023-11-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjeong HWANG ,  Kyung Don MUN ,  Kyoung Lim SUK

    IPC: H01L25/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

    CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L28/10 ,  H10B80/00

    Abstract: A semiconductor package including a first semiconductor structure on a first redistribution layer structure; first conductive posts on the first redistribution layer structure and next to the first side of the first semiconductor structure; second conductive posts on the first redistribution layer structure and next to a second side opposite to the first side of the first semiconductor structure; a molding material molding the first semiconductor structure, the first conductive posts, and the second conductive posts on the first redistribution layer structure; a second redistribution layer structure on the molding material; a second semiconductor structure on the second redistribution layer structure; a heat dissipation structure on the second redistribution layer structure; and a 3D solenoid inductor including some of the second conductive posts, the redistribution lines at the uppermost of the first redistribution layer structure, and the redistribution lines at the lowermost of the second redistribution layer structure.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230068587A1

    公开(公告)日：2023-03-02

    申请号：US17853205

    申请日：2022-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yae Jung YOON ,  Eung Kyu KIM ,  Min Jun BAE ,  Kyoung Lim SUK ,  Seok Hyun LEE ,  Jae Gwon JANG

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/053

    Abstract: A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
    5.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190035756A1

    公开(公告)日：2019-01-31

    申请号：US15867075

    申请日：2018-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUN JI MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

    IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

    Abstract: A method of fabricating a semiconductor package including, forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230033087A1

    公开(公告)日：2023-02-02

    申请号：US17682465

    申请日：2022-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoung Lim SUK ,  Taewon YOO ,  Seokhyun LEE

    IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

    Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate including a first, second and third under-bump patterns; a semiconductor chip provided on the first substrate; conductive structures provided on the first substrate; and a second substrate provided on the semiconductor chip and the conductive structures. The third under-bump pattern is electrically isolated from the first and second under-bump patterns. The conductive structures include: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and provided adjacent to the first and second conductive structures. The third conductive structure is provided between the first conductive structure and the second conductive structure, the first under-bump pattern is wider than the third under-bump pattern, and the second under-bump pattern is wider than the third under-bump pattern.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220293501A1

    公开(公告)日：2022-09-15

    申请号：US17453243

    申请日：2021-11-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaegwon JANG ,  Kyoung Lim SUK ,  Minjun BAE

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

    SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE
    10.
    发明公开
    SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE 审中-公开

    公开(公告)号：US20240021608A1

    公开(公告)日：2024-01-18

    申请号：US18478056

    申请日：2023-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoung Lim SUK ,  Seokhyun LEE ,  Jaegwon JANG

    IPC: H01L27/08 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L27/0805 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/14 ,  H01L28/60

    Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal

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