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公开(公告)号：US20240332268A1
公开(公告)日：2024-10-03
申请号：US18739690
申请日：2024-06-11
发明人： KYOUNG LIM SUK , SEOKHYUN LEE
IPC分类号： H01L25/10 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/528
CPC分类号： H01L25/105 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5226 , H01L23/5283 , H01L24/08 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/96 , H01L24/97 , H01L2224/0231 , H01L2224/02373 , H01L2224/02381 , H01L2224/08235 , H01L2224/16227 , H01L2224/96 , H01L2224/97 , H01L2225/1041 , H01L2225/1058 , H01L2924/182
摘要： A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.
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公开(公告)号：US20240030119A1
公开(公告)日：2024-01-25
申请号：US18374396
申请日：2023-09-28
发明人： DONGKYU KIM , SEOKHYUN LEE , KYOUNG LIM SUK , JAEGWON JANG , GWANGJAE JEON
IPC分类号： H01L23/498 , H01L23/00 , H01L25/065
CPC分类号： H01L23/49822 , H01L24/32 , H01L24/16 , H01L23/49833 , H01L25/0657 , H01L23/49894 , H01L2224/16227 , H01L2224/32225
摘要： A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.
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公开(公告)号：US20230230965A1
公开(公告)日：2023-07-20
申请号：US18125170
申请日：2023-03-23
发明人： DONGKYU KIM , SEOKHYUN LEE , YEONHO JANG , JAEGWON JANG
IPC分类号： H01L25/10 , H01L23/00 , H01L21/56 , H01L23/538 , H01L21/48 , H01L25/00 , H01L23/31 , H01L21/683
CPC分类号： H01L25/105 , H01L24/19 , H01L21/563 , H01L23/562 , H01L23/5383 , H01L24/48 , H01L21/4857 , H01L25/50 , H01L21/565 , H01L23/3135 , H01L21/568 , H01L24/20 , H01L21/6835 , H01L23/3128 , H01L23/5386 , H01L21/4853 , H01L23/5389 , H01L2224/214 , H01L2225/1058 , H01L2225/1041 , H01L2225/1035 , H01L2924/3511 , H01L2924/01029 , H01L2221/68372 , H01L2224/48227 , H01L2924/01079 , H01L2924/01028 , H01L2224/215
摘要： A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.
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公开(公告)号：US20200083201A1
公开(公告)日：2020-03-12
申请号：US16430426
申请日：2019-06-04
发明人： KYOUNG LIM SUK , SEOKHYUN LEE
IPC分类号： H01L25/10 , H01L23/522 , H01L23/528 , H01L23/31 , H01L21/56 , H01L23/00
摘要： A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.
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公开(公告)号：US20240071866A1
公开(公告)日：2024-02-29
申请号：US18237209
申请日：2023-08-23
发明人： CHEOL KIM , SEOKHYUN LEE
IPC分类号： H01L23/433 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/10
CPC分类号： H01L23/4334 , H01L23/3128 , H01L23/49822 , H01L24/24 , H01L25/105 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/2101 , H01L2224/32225 , H01L2224/73204
摘要： A semiconductor package includes a package substrate, a first semiconductor chip, and an encapsulant surrounding the semiconductor chip. The first semiconductor chip includes a semiconductor substrate having an active surface and an inactive surface opposite to the active surface, the semiconductor chip disposed on the package substrate such that the active surface faces the package substrate. The semiconductor package further includes a first redistribution structure on the encapsulant. The first redistribution structure includes a thermally conductive pattern, a heat-conducting through via providing a path for heat to conduct from the semiconductor substrate to the thermally conductive pattern, and a redistribution insulating layer surrounding the heat-conducting through via. The semiconductor substrate includes a first contact region having a higher temperature than a surrounding area on the inactive surface, and the heat-conducting through via passes through the encapsulant and contacts the first contact region.
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公开(公告)号：US20230215799A1
公开(公告)日：2023-07-06
申请号：US18183062
申请日：2023-03-13
发明人： KYOUNG LIM SUK , KEUNG BEUM KIM , DONGKYU KIM , MINJUNG KIM , SEOKHYUN LEE
IPC分类号： H01L23/498 , H01L25/10 , H01L23/538 , H01L21/48 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L23/49838 , H01L23/49816 , H01L25/105 , H01L23/5386 , H01L23/5383 , H01L23/49822 , H01L21/4857 , H01L2924/14361 , H01L24/16 , H01L24/73 , H01L24/17 , H01L2924/1431 , H01L2224/08225 , H01L2924/1433 , H01L24/08 , H01L2225/1035 , H01L2224/16227 , H01L25/0652 , H01L25/18 , H01L24/33 , H01L2224/17181 , H01L2224/73253 , H01L2225/1058 , H01L2224/33181 , H01L2224/73204
摘要： A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.
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公开(公告)号：US20230065378A1
公开(公告)日：2023-03-02
申请号：US17680857
申请日：2022-02-25
发明人： MINJUNG KIM , DONGKYU KIM , JONGYOUN KIM , SEOKHYUN LEE
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48 , H01L23/498
摘要： A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.
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公开(公告)号：US20230065366A1
公开(公告)日：2023-03-02
申请号：US17806907
申请日：2022-06-14
发明人： DONGKYU KIM , MINJUNG KIM , KYOUNG LIM SUK , SEOKHYUN LEE
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48 , H01L23/31 , H01L23/498
摘要： A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.
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公开(公告)号：US20220084993A1
公开(公告)日：2022-03-17
申请号：US17239956
申请日：2021-04-26
发明人： DONGKYU KIM , SEOKHYUN LEE , YEONHO JANG , JAEGWON JANG
IPC分类号： H01L25/10 , H01L23/00 , H01L23/31 , H01L23/538 , H01L21/683 , H01L21/48 , H01L21/56 , H01L25/00
摘要： A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.
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公开(公告)号：US20210398890A1
公开(公告)日：2021-12-23
申请号：US17177305
申请日：2021-02-17
发明人： DONGKYU KIM , SEOKHYUN LEE , KYOUNG LIM SUK , JAEGWON JANG , GWANGJAE JEON
IPC分类号： H01L23/498 , H01L23/00 , H01L25/065
摘要： A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.
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