公开(公告)号：US20180175001A1

公开(公告)日：2018-06-21

申请号：US15837187

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun PYO ,  Jongbo SHIM ,  Ji Hwang KIM ,  Chajea JO ,  Sang-Uk HAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/15311

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US20250046691A1

公开(公告)日：2025-02-06

申请号：US18544707

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Kyung Don MUN ,  Sangjin BAEK ,  Hyeonjeong HWANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first redistribution line structure; a first semiconductor chip on one surface of the first redistribution line structure; a first conductive bump between, and connecting, the first redistribution line structure and the first semiconductor chip; a first encapsulant encapsulating at least a portion of the first semiconductor chip; a second semiconductor chip on another, opposite surface of the first redistribution line and including a through via; a second conductive bump between, and connecting, the first redistribution line structure and the second semiconductor chip; a second encapsulant encapsulating at least a portion of the second semiconductor chip; and a second redistribution line structure on the second encapsulant. The second encapsulant covers at least a portion of a surface of the second semiconductor chip facing the second redistribution line structure.

公开(公告)号：US20140141569A1

公开(公告)日：2014-05-22

申请号：US14018630

申请日：2013-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ji Hwang KIM ,  Tae Hong MIN ,  Tae-Sub CHANG ,  Taeje CHO

IPC: H01L21/768 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552

Abstract: In a method of fabricating a semiconductor device, a first sacrificial through-via is formed to fill a first via-hole extending from a first surface of a first substrate toward a second surface of the first substrate opposite the first surface. The first surface of the first substrate is bonded to a carrier. The first sacrificial through-via is exposed, and the first sacrificial through-via is selectively removed. After selectively removing the first sacrificial through-via, a conductive through-via is formed to fill the first via-hole.

Abstract translation: 在制造半导体器件的方法中，形成第一牺牲通孔以填充从第一衬底的第一表面朝向与第一表面相对的第一衬底的第二表面延伸的第一通孔。 第一衬底的第一表面被结合到载体上。 第一牺牲通孔被暴露，并且选择性地去除第一牺牲通孔。 在选择性地去除第一牺牲通孔之后，形成导电通孔以填充第一通孔。

公开(公告)号：US20140038353A1

公开(公告)日：2014-02-06

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Tae Hong MIN ,  Chajea JO ,  Taeje CHO ,  Young Kun JEE ,  Yun Seok CHOI

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。

公开(公告)号：US20220173082A1

公开(公告)日：2022-06-02

申请号：US17407647

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho KIM ,  Ji Hwang KIM ,  Hwan Pil PARK ,  Jongbo SHIM

IPC: H01L25/10 ,  H01L25/065 ,  H01L21/48

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

公开(公告)号：US20190259733A1

公开(公告)日：2019-08-22

申请号：US16404066

申请日：2019-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun PYO ,  Jongbo SHIM ,  Ji Hwang KIM ,  Chajea JO ,  Sang-Uk HAN

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US20140148007A1

公开(公告)日：2014-05-29

申请号：US14170062

申请日：2014-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Sunpil YOUN ,  Sangwon KIM ,  Kwang-chul CHOI ,  Tae Hong MIN

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.

Abstract translation: 半导体器件包括具有第一侧和第二侧的基板，使得第一和第二面彼此面对，贯穿基板的通孔塞，绝缘膜衬垫和防污染膜。 绝缘膜衬垫位于通孔插塞和衬底之间，并且绝缘膜衬套相对于第二侧具有凹陷表面。 防污染膜覆盖第二面，防污染膜位于凹陷表面上，并且在通孔插塞和基底之间。

公开(公告)号：US20240363472A1

公开(公告)日：2024-10-31

申请号：US18768963

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20230207416A1

公开(公告)日：2023-06-29

申请号：US18178170

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo Shim ,  Jang Woo Lee ,  Yung Cheol Kong ,  Young Hoon Hyun

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20230111343A1

公开(公告)日：2023-04-13

申请号：US17961954

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Bin YIM ,  Ji Hwang KIM ,  Jin-woo PARK ,  Jong Bo SHIM

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.