公开(公告)号：US20240105567A1

公开(公告)日：2024-03-28

申请号：US18454464

申请日：2023-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choong Bin YIM ,  Ji Yong PARK ,  Jong Bo SHIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1433 ,  H01L2924/3511

Abstract: A semiconductor package includes a first package substrate having a first area and a second area that is distinct and separate from the first area, a first connection element disposed on the first area and having a first thickness, a first semiconductor chip connected to the first connection element, a second connection element disposed on the second area and having a second thickness that is greater than the first thickness, a third connection element disposed on the second connection element and electrically connected to the second connection element, a second package substrate disposed on the third connection element, and a second semiconductor chip disposed on the second package substrate.

公开(公告)号：US20180040590A1

公开(公告)日：2018-02-08

申请号：US15435285

申请日：2017-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Ho CHANG ,  Jong Bo SHIM ,  Cha Je JO

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0912 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad and a second pad different from the first pad, the first pad and the second pad being disposed on a first surface of the first semiconductor chip; a metal line disposed on the substrate and the first semiconductor chip and electrically connecting the first pad of the first semiconductor chip with the external connection terminal of the substrate; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a third pad disposed on a second surface of the second semiconductor chip facing the first semiconductor chip; and a connection terminal electrically connecting the second pad of the first semiconductor chip with the third pad of the second semiconductor chip, the connection terminal being not electrically connected to the metal line.

公开(公告)号：US20240363472A1

公开(公告)日：2024-10-31

申请号：US18768963

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20230111343A1

公开(公告)日：2023-04-13

申请号：US17961954

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Bin YIM ,  Ji Hwang KIM ,  Jin-woo PARK ,  Jong Bo SHIM

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.

公开(公告)号：US20230076184A1

公开(公告)日：2023-03-09

申请号：US17875949

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Bo SHIM ,  Sung Bum KIM ,  Ji Hwang KIM

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31

Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

公开(公告)号：US20210343617A1

公开(公告)日：2021-11-04

申请号：US17376570

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.