公开(公告)号：US20240363472A1

公开(公告)日：2024-10-31

申请号：US18768963

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20210343617A1

公开(公告)日：2021-11-04

申请号：US17376570

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20200227131A1

公开(公告)日：2020-07-16

申请号：US16537970

申请日：2019-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Hoon NA ,  Jang Woo LEE ,  Jin Do BYUN ,  Jeong Don IHM

IPC: G11C29/50 ,  H01L25/065 ,  H01L25/18

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

公开(公告)号：US20190214064A1

公开(公告)日：2019-07-11

申请号：US16033691

申请日：2018-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Woo LEE ,  Jeong Don IHM ,  Byung Hoon JEONG

IPC: G11C7/22

CPC classification number: G11C7/225 ,  G11C7/1093 ,  G11C7/227 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit.