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    CHIP-ON-FILM PACKAGE
    3.
    发明申请
    CHIP-ON-FILM PACKAGE 有权

    公开(公告)号：US20230037785A1

    公开(公告)日：2023-02-09

    申请号：US17699525

    申请日：2022-03-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： KwanJai LEE ,  Jae-Min JUNG ,  Jeong-Kyu HA ,  Sang-Uk HAN

    IPC分类号： H01L23/498 ,  H01L23/00

    摘要： A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190259733A1

    公开(公告)日：2019-08-22

    申请号：US16404066

    申请日：2019-05-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sungeun PYO ,  Jongbo SHIM ,  Ji Hwang KIM ,  Chajea JO ,  Sang-Uk HAN

    IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

    摘要： A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

    SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER
    5.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER 审中-公开
    具有热交换器的半导体封装

    公开(公告)号：US20150137345A1

    公开(公告)日：2015-05-21

    申请号：US14504309

    申请日：2014-10-01

    申请人： Samsung Electronics Co., Ltd.

    发明人： Eun-Kyoung CHOI ,  Sang-Uk HAN ,  Tae-Je CHO

    IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/367

    CPC分类号： H01L25/0657 ,  H01L23/04 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability.

    摘要翻译： 半导体封装包括散热器。 半导体封装包括衬底，设置在衬底上的第一半导体芯片和设置在第一半导体芯片上的第二半导体芯片。 散热器可以形成在第一半导体芯片上。 热界面材料（TIM）层可以形成为与第一半导体芯片和散热器接触并且可以覆盖第二半导体芯片的侧表面。 可以通过TIM层和散热器发射由第一半导体芯片产生的热量。 可以分配由基板和第一半导体芯片之间的热膨胀系数（CTE）引起的热应力，以确保结构稳定性。

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20140252605A1

    公开(公告)日：2014-09-11

    申请号：US14198713

    申请日：2014-03-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Keum-Hee MA ,  Cha-Jea JO ,  Sang-Uk HAN

    IPC分类号： H01L25/00 ,  H01L25/065

    CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568

    摘要： Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate.

    摘要翻译： 提供半导体封装及其制造方法。 制造半导体封装的方法包括将多个第二半导体芯片和多个第一半导体芯片中的每一个布置在包括多个第一半导体芯片的第一晶片上彼此电连接，第一宽度 所述第一半导体芯片中的每一个大于所述第二半导体芯片的第二宽度，形成围绕所述第一晶片上的所述第二半导体芯片的第一模制层，通过锯切所述第一半导体芯片形成包括所述第一和第二半导体芯片的芯片封装 以第一半导体芯片为单位的第一晶片，将芯片封装布置在封装衬底上，以将第二半导体芯片电连接到封装衬底，以及在封装衬底上形成围绕芯片封装的第二模制层。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220165652A1

    公开(公告)日：2022-05-26

    申请号：US17391164

    申请日：2021-08-02

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Uk HAN ,  Duck Gyu KIM ,  Min Ki KIM ,  Jae-Min JUNG ,  Jeong-Kyu HA

    IPC分类号： H01L23/498 ,  H01L23/58

    摘要： A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.