公开(公告)号：US20220165652A1

公开(公告)日：2022-05-26

申请号：US17391164

申请日：2021-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk HAN ,  Duck Gyu KIM ,  Min Ki KIM ,  Jae-Min JUNG ,  Jeong-Kyu HA

IPC: H01L23/498 ,  H01L23/58

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

公开(公告)号：US20250140677A1

公开(公告)日：2025-05-01

申请号：US18739665

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Jeong SHIN ,  Duck Gyu KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate including a first surface and a second surface, which are opposite to each other in a first direction, a semiconductor chip mounted on the first surface of the redistribution substrate, a redistribution pattern in the redistribution substrate and electrically connected to the semiconductor chip, a metal pattern electrically connected to the redistribution pattern, including a third surface and a fourth surface, which are opposite to each other in the first direction, and a connection terminal on the second surface of the redistribution substrate and being in contact with the fourth surface of the metal pattern, wherein at least a portion of the redistribution pattern is in contact with sidewalls of the metal pattern, wherein the third surface faces the semiconductor chip and is not in contact with the redistribution pattern, and wherein the fourth surface does not overlap the second surface in the first direction.