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公开(公告)号:US20240162111A1
公开(公告)日:2024-05-16
申请号:US18510056
申请日:2023-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seunghyun CHO , Jae-Min JUNG
IPC: H01L23/373 , H01L23/00 , H01L23/538 , H01L25/11
CPC classification number: H01L23/3737 , H01L23/5383 , H01L23/5387 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/115 , H01L2224/14177 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203
Abstract: A semiconductor package includes a flexible insulating substrate including a first surface and a second surface opposite to the first surface, a first wiring on the first surface of the flexible insulating substrate, a second wiring on the second surface of the flexible insulating substrate, a plurality of vias coupling the first wiring to the second wiring, a plurality of semiconductor devices on the first surface of the flexible insulating substrate, and a heat dissipation resin layer at least partially covering at least one semiconductor device of the plurality of semiconductor devices.
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公开(公告)号:US20140328031A1
公开(公告)日:2014-11-06
申请号:US14262658
申请日:2014-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: KYOUNGSUK YANG , Jeong-Kyu HA , PaLan LEE , NARAE SHIN , Soyoung LIM , Jae-Min JUNG , KyongSoon CHO
CPC classification number: H05K1/118 , H05K1/147 , H05K1/189 , H05K2201/0949 , H05K2201/10128
Abstract: Provided is a display apparatus. The display apparatus includes a display panel, a flexible circuit film having a rear surface connected to the display panel, and a front surface opposite to the rear surface, the front surface having a chip mounted thereon, and a first lead bonding portion electrically connecting the chip to the display panel. The first lead bonding portion includes a first portion connected to the chip and overlying a portion of the flexible circuit film, a second portion passing through the flexible circuit film, and a third portion disposed between the flexible circuit film and the display panel on the rear surface of the flexible circuit film, where the third portion overlaps the first portion.
Abstract translation: 提供了一种显示装置。 显示装置包括显示面板,具有连接到显示面板的后表面的柔性电路薄膜和与背面相对的前表面,前表面具有安装在其上的芯片,以及第一引线接合部分, 芯片到显示面板。 第一引线接合部分包括连接到芯片并覆盖柔性电路膜的一部分的第一部分,穿过柔性电路膜的第二部分和设置在柔性电路膜和后面的显示面板之间的第三部分 柔性电路膜的表面,其中第三部分与第一部分重叠。
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公开(公告)号:US20210398870A1
公开(公告)日:2021-12-23
申请号:US17462269
申请日:2021-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung-Tae HWANG , Jae-Choon KIM , Kyung-Suk OH , Woon-Bae KIM , Jae-Min JUNG
IPC: H01L23/31 , H01L23/498 , H05K1/14
Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.
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公开(公告)号:US20250167189A1
公开(公告)日:2025-05-22
申请号:US18888923
申请日:2024-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Min JUNG , Seung Hyun Cho
IPC: H01L33/62
Abstract: A display device including: a thin film substrate; a display substrate connected to a first side of the thin film substrate; a light emitting element layer on an upper surface of the display substrate; a circuit board connected to a second side of the thin film substrate opposite the first side of the thin film substrate in a first horizontal direction; a metal pattern on the thin film substrate, wherein the metal pattern does not overlap a first portion of the thin film substrate connected to the display substrate and does not overlap a second portion of the thin film substrate connected to the circuit board in a vertical direction, wherein the metal pattern includes a metal, and wherein the metal pattern is electrically insulated from the thin film substrate; and a pattern region, wherein the metal pattern is around the pattern region.
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公开(公告)号:US20230037785A1
公开(公告)日:2023-02-09
申请号:US17699525
申请日:2022-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: KwanJai LEE , Jae-Min JUNG , Jeong-Kyu HA , Sang-Uk HAN
IPC: H01L23/498 , H01L23/00
Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.
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公开(公告)号:US20200211973A1
公开(公告)日:2020-07-02
申请号:US16814528
申请日:2020-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Min JUNG , JiAh MIN
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/552 , H01L23/00
Abstract: A film package includes a film substrate, a first semiconductor chip on a first surface of the film substrate, a second semiconductor chip on the first surface of the film substrate, and a first conductive film on the first surface of the film substrate. The first conductive film covers the first semiconductor chip and the second semiconductor chip and includes a slit(s) or a notch(es). The slit(s) or notch(es) is/are disposed in a bridge region between the first semiconductor chip and the second semiconductor chip, in a plan view of the package.
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公开(公告)号:US20160049356A1
公开(公告)日:2016-02-18
申请号:US14714234
申请日:2015-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jae-Min JUNG , Jeong-Kyu HA
IPC: H01L23/498 , H01L25/065
CPC classification number: H01L23/4985 , G02F1/13452 , G02F1/13458 , H01L23/481 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/83 , H01L24/86 , H01L2224/13144 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2224/81424 , H01L2224/81447 , H01L2224/81455 , H01L2224/83104 , H01L2224/83862 , H01L2224/86203 , H01L2924/00014 , H05K1/028 , H05K1/112 , H05K1/118 , H05K1/189 , H05K2201/055 , H05K2201/09227 , H05K2201/10128 , H05K2201/10674 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
Abstract: A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection.
Abstract translation: 片上胶卷包装包括一个包括上表面和下表面的薄膜基材和一个具有弯曲部分的一面。 形成在薄膜基板的上表面上的第一输出互连件从设置在上表面上的半导体芯片朝向弯曲部分延伸。 第二输出互连包括形成在薄膜基板的上表面上的上输出互连和形成在下表面上并延伸到弯曲部上的下输出互连。 输入互连包括形成在薄膜基板的上表面上的上输入互连和形成在下表面上并且远离弯曲部延伸的下输入互连。 通孔形成为通过薄膜基板并将上部输出互连电连接到下部输出互连,并将上部输入互连电连接到下部输入互连。
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公开(公告)号:US20240096904A1
公开(公告)日:2024-03-21
申请号:US18459766
申请日:2023-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Min JUNG , Seung Hyun CHO
IPC: H01L27/12
CPC classification number: H01L27/124
Abstract: A chip-on-film package includes: a lower base film including a first surface and a second surface, which are opposite to each other; an upper base film including a third surface and a fourth surface, which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip mounted on the second surface of the lower base film; a second semiconductor chip mounted on the third surface of the upper base film; and an interposer film interposed between the lower and upper base films, wherein the second and third surfaces face each other.
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公开(公告)号:US20240079312A1
公开(公告)日:2024-03-07
申请号:US18505613
申请日:2023-11-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: KwanJai LEE , Jae-Min JUNG , Jeong-Kyu HA , Sang-Uk HAN
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/4985 , H01L23/49838 , H01L23/49894 , H01L24/73 , H01L2224/73204
Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.
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公开(公告)号:US20220165652A1
公开(公告)日:2022-05-26
申请号:US17391164
申请日:2021-08-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sang-Uk HAN , Duck Gyu KIM , Min Ki KIM , Jae-Min JUNG , Jeong-Kyu HA
IPC: H01L23/498 , H01L23/58
Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.
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