公开(公告)号：US20200006242A1

公开(公告)日：2020-01-02

申请号：US16201380

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun JEE ,  II Hwan KIM ,  Un Byoung KANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US20150093857A1

公开(公告)日：2015-04-02

申请号：US14566685

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihwan HWANG ,  Young Kun JEE ,  Jung-Hwan KIM ,  Tae Hong MIN ,  Kwang-chul CHOI

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract translation: 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。

公开(公告)号：US20140038353A1

公开(公告)日：2014-02-06

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Tae Hong MIN ,  Chajea JO ,  Taeje CHO ,  Young Kun JEE ,  Yun Seok CHOI

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。

公开(公告)号：US20220130802A1

公开(公告)日：2022-04-28

申请号：US17571796

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho JUN ,  Un-Byoung KANG ,  Sunkyoung SEO ,  Jongho LEE ,  Young Kun JEE

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US20210020578A1

公开(公告)日：2021-01-21

申请号：US17036702

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun JEE ,  Il Hwan KIM ,  Un Byoung KANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US20240332256A1

公开(公告)日：2024-10-03

申请号：US18382807

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Young Kun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate including a mounting region and an edge region at least partially surrounding the mounting region, a bridge chip on a top surface of the mounting region of the package substrate, a first connection pad and a second connection pad on the mounting region of the package substrate and spaced apart from the bridge chip, a third connection pad on the edge region of the package substrate, a first mold layer on the package substrate and at least partially surrounding the bridge chip, the first connection pad, the second connection pad and the third connection pad, a first semiconductor chip on the first connection pad and the bridge chip, a second semiconductor chip on the second connection pad and the bridge chip, and a conductive post on the third connection pad.

公开(公告)号：US20240170459A1

公开(公告)日：2024-05-23

申请号：US18502569

申请日：2023-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Hee HWANG ,  Young Kun JEE ,  Sang Cheon PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/1436 ,  H10B80/00

Abstract: A semiconductor package may include a package substrate, a stack die including a plurality of dies are stacked on the package substrate, a gap fill insulating layer on an upper surface of the stack die, a top dummy die on the gap fill insulating layer, and a molding portion surrounding the stack die having the top dummy die thereon.

公开(公告)号：US20240014177A1

公开(公告)日：2024-01-11

申请号：US18217701

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Kun JEE ,  Un-Byoung KANG ,  Jum Yong PARK ,  Jong-Hyeon CHANG

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L24/16 ,  H01L23/481 ,  H01L24/19 ,  H01L2225/06544 ,  H01L2224/20 ,  H01L2224/16145 ,  H01L2924/15311

Abstract: A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.

公开(公告)号：US20210183816A1

公开(公告)日：2021-06-17

申请号：US16936882

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho JUN ,  Un-Byoung KANG ,  Sunkyoung SEO ,  Jongho LEE ,  Young Kun JEE

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.