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    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230049283A1

    公开(公告)日：2023-02-16

    申请号：US17730551

    申请日：2022-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyounglim SUK ,  Daewoo Kim ,  Seokhyun Lee

    IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56

    Abstract: A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD
    2.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD 有权

    公开(公告)号：US20220328388A1

    公开(公告)日：2022-10-13

    申请号：US17508250

    申请日：2021-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjeong HWANG ,  Kyounglim SUK ,  Seokhyun LEE

    IPC: H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

    SEMICONDUCTOR PACKAGE
    3.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240113001A1

    公开(公告)日：2024-04-04

    申请号：US18212939

    申请日：2023-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyounglim SUK ,  Jihwang Kim ,  Suchang Lee ,  Hyeonjeong Hwang

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

    CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227

    Abstract: A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230071812A1

    公开(公告)日：2023-03-09

    申请号：US17846245

    申请日：2022-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegwon JANG ,  Kyounglim SUK ,  Inhyung SONG

    IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220037306A1

    公开(公告)日：2022-02-03

    申请号：US17190689

    申请日：2021-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seho YOU ,  Kyounglim SUK

    IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

    Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240145396A1

    公开(公告)日：2024-05-02

    申请号：US18381711

    申请日：2023-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sehoon JANG ,  Hyeonjeong HWANG ,  Kyounglim SUK

    IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

    CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16

    Abstract: A semiconductor package includes a base substrate. An interposer substrate includes a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer. The plurality of interposer redistribution structures includes a plurality of conductive interposer patterns and a plurality of conductive interposer vias. A semiconductor chip is disposed between the base substrate and the interposer substrate and is attached on the base substrate. A plurality of conductive connection pads is respectively disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures. The interposer insulation layer includes a plurality of pad holes exposing at least a portion of each of an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns.

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