公开(公告)号：US11315886B2

公开(公告)日：2022-04-26

申请号：US16848106

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung Choi ,  Suchang Lee ,  Yunseok Choi

IPC: H01L23/16 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

公开(公告)号：US11315849B2

公开(公告)日：2022-04-26

申请号：US17060805

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suchang Lee ,  Dongok Kwak

IPC: H01L23/36 ,  H01L23/538

Abstract: A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.

公开(公告)号：US20240113001A1

公开(公告)日：2024-04-04

申请号：US18212939

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounglim SUK ,  Jihwang Kim ,  Suchang Lee ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227

Abstract: A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

公开(公告)号：US11776918B2

公开(公告)日：2023-10-03

申请号：US17705770

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung Choi ,  Suchang Lee ,  Yunseok Choi

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.