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公开(公告)号：US20240234235A9
公开(公告)日：2024-07-11
申请号：US18381637
申请日：2023-10-19
发明人： Yenheng CHEN , Chengchung LIN
IPC分类号： H01L23/367 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/498
CPC分类号： H01L23/3675 , H01L21/561 , H01L21/76882 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/13 , H01L2224/05009 , H01L2224/05025 , H01L2224/13025 , H01L2224/131 , H01L2924/01006 , H01L2924/01013 , H01L2924/182 , H01L2924/351
摘要： A thermally conductive semiconductor packaging structure includes a cooling component exposed on one surface and an electrical interconnecting component on the other surface. The cooling component has a thermally conductive die, its back side is provided with thermally conductive members extending away from the back side, and a front side is provided with pads to connect to the electrical interconnecting component. The electrical interconnecting component includes electrically conductive connectors to connect to the thermally conductive die, a rewiring layer, and metal bumps connecting to the rewiring layer. A substrate, electrically connected to the metal bumps and a heat dissipating cover over the substrate and in contact with the thermally conductive members. The package is applicable to a wide range of packages.
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公开(公告)号：US20240136245A1
公开(公告)日：2024-04-25
申请号：US18381637
申请日：2023-10-18
发明人： Yenheng CHEN , Chengchung LIN
IPC分类号： H01L23/367 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/498
CPC分类号： H01L23/3675 , H01L21/561 , H01L21/76882 , H01L23/49816 , H01L23/49822 , H01L24/05 , H01L24/13 , H01L2224/05009 , H01L2224/05025 , H01L2224/13025 , H01L2224/131 , H01L2924/01006 , H01L2924/01013 , H01L2924/182 , H01L2924/351
摘要： A thermally conductive semiconductor packaging structure includes a cooling component exposed on one surface and an electrical interconnecting component on the other surface. The cooling component has a thermally conductive die, its back side is provided with thermally conductive members extending away from the back side, and a front side is provided with pads to connect to the electrical interconnecting component. The electrical interconnecting component includes electrically conductive connectors to connect to the thermally conductive die, a rewiring layer, and metal bumps connecting to the rewiring layer. A substrate, electrically connected to the metal bumps and a heat dissipating cover over the substrate and in contact with the thermally conductive members. The package is applicable to a wide range of packages.
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公开(公告)号：US20230386967A1
公开(公告)日：2023-11-30
申请号：US18142424
申请日：2023-05-02
发明人： Chengchung Lin , Jin Yang
IPC分类号： H01L23/473 , H01L25/065 , H01L25/18 , H10B80/00
CPC分类号： H01L23/473 , H01L25/0655 , H01L25/18 , H10B80/00
摘要： A wafer packaging system and a method for manufacturing the same are disclosed; the system comprises: a silicon substrate having a first surface and a second surface opposite to the first surface; a rewiring layer disposed on the first surface of the silicon substrate; a plurality of chips bonded over the rewiring layer; and a structural reinforcement layer, fixed to the second surface of the silicon substrate, wherein liquid cooling channels are formed inside the structural reinforcement layer. The wafer packaging system of the present disclosure integrates a plurality of chips with different functions onto one full-wafer-size platform to improve the packaging performance. A structural reinforcement layer is added to the packaging system, which supports a large silicon substrate platform and enhances the structural rigidity of the whole packaging system. The structural reinforcement layer, along with liquid cooling channels, provides a heat conducting path for heat generated by the system.
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公开(公告)号：US11502392B2
公开(公告)日：2022-11-15
申请号：US17108953
申请日：2020-12-01
发明人： Yenheng Chen , Chengchung Lin , Chengtar Wu , Jangshen Lin
IPC分类号： H01L23/34 , H01Q1/22 , H01L23/66 , H01L23/00 , H01L23/498 , H01L21/48 , H01L21/683
摘要： The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.
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公开(公告)号：US11380649B2
公开(公告)日：2022-07-05
申请号：US17207368
申请日：2021-03-19
发明人： Hailin Zhao
摘要： The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.
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6.发明申请公开(公告)号：US20220165654A1
公开(公告)日：2022-05-26
申请号：US17531631
申请日：2021-11-19
发明人： Yenheng CHEN , Chengchung Lin
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L23/48 , H01L23/29
摘要： A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.
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公开(公告)号：US20220084925A1
公开(公告)日：2022-03-17
申请号：US17476340
申请日：2021-09-15
发明人： Yenheng CHEN , Chengchung Lin
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L25/10
摘要： The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be significantly shortened, thereby reducing the power consumption, increasing the signal transmission speed, and increasing the data processing capacity.
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公开(公告)号：US11121065B2
公开(公告)日：2021-09-14
申请号：US16232988
申请日：2018-12-26
发明人： Yenheng Chen , Chentar Wu , Chengchung Lin
IPC分类号： H01L23/498 , H01L23/15 , H01L23/31 , H01L23/66
摘要： The present application provides a semiconductor packaging structure with an antenna assembly, including: a substrate with through-substrate-via holes; a rewiring layer, located on the substrate; metal bumps, located on and electrically connected to the rewiring layer; a semiconductor chip, located on a surface of the rewiring layer and electrically connected to the rewiring layer; a conductive column, filling in the via hole; a bottom filling layer filling up a gap between the semiconductor chip and the rewiring layer; a polymer layer surrounding the metal bumps and the semiconductor chip; and an antenna assembly, which is electrically connected to one metal bump through the conductive column and the rewiring layer. By using the foregoing solution, the rewiring layer and the metal bumps facilitate proper packaging design.
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公开(公告)号：US20210066784A1
公开(公告)日：2021-03-04
申请号：US16936015
申请日：2020-07-22
发明人： Chengtar WU , Rui YU , Chengchung LIN , Xianghui ZHANG
摘要： The present disclosure provides an antenna packaging module and the making method. The antenna packaging module comprises a redistribution layer, an antenna structure, a semiconductor chip, a third packaging layer, and a packaging antenna connector to an external circuit board. The antenna structure includes a connector opening and at least a first antenna structure and a second antenna structure stacked on one surface of the redistribution layer. The packaging antenna connector is designed in the connector opening and is electrically connected to the redistribution layer. Electrical terminals are provided through the packaging antenna connector disposed in the connector opening, thus reducing the antenna signal loss. The antenna packaging module requires neither any metal wire ends electrically connected to redistribution layer, nor a flip-chip process.
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公开(公告)号：US10886243B2
公开(公告)日：2021-01-05
申请号：US16674902
申请日：2019-11-05
发明人： Yenheng Chen , Chengchung Lin , Chengtar Wu , Jangshen Lin
IPC分类号： H01L23/66 , H01L21/48 , H01L23/00 , H01L21/56 , H01L23/538 , H01L23/367 , H01L23/31 , H01Q1/22 , H01Q1/02 , H01L21/683 , H01L23/13
摘要： A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip.
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